Lines Matching +full:0 +full:x55000000
22 #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
24 #define CONFIG_NVS_LOCATION 0xf4800000
28 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
29 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
30 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
31 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
32 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
33 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
40 return 0; in hws_board_topology_load()
50 0x1, /* active interfaces */
52 { { { {0x1, 0, 0, 0},
53 {0x1, 0, 0, 0},
54 {0x1, 0, 0, 0},
55 {0x1, 0, 0, 0},
56 {0x1, 0, 0, 0} },
61 0, 0, /* cas_l cas_wl */
66 { {0} }, /* raw spd data */
67 {0} /* timing parameters */
79 writel(0x00001111, MVEBU_MPP_BASE + 0x00); in board_early_init_f()
80 writel(0x00000000, MVEBU_MPP_BASE + 0x04); in board_early_init_f()
81 writel(0x55000000, MVEBU_MPP_BASE + 0x08); in board_early_init_f()
82 writel(0x55550550, MVEBU_MPP_BASE + 0x0c); in board_early_init_f()
83 writel(0x55555555, MVEBU_MPP_BASE + 0x10); in board_early_init_f()
84 writel(0x00100565, MVEBU_MPP_BASE + 0x14); in board_early_init_f()
85 writel(0x40000000, MVEBU_MPP_BASE + 0x18); in board_early_init_f()
86 writel(0x00004444, MVEBU_MPP_BASE + 0x1c); in board_early_init_f()
88 return 0; in board_early_init_f()
94 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; in board_init()
101 writel(0x00004001, MVEBU_DEV_BUS_BASE + 0xc8); in board_init()
103 return 0; in board_init()
113 node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, in led_7seg_init()
115 if (node < 0) in led_7seg_init()
121 if (ret < 0) in led_7seg_init()
124 for (i = 0; i < ARRAY_SIZE(desc); i++) { in led_7seg_init()
130 return 0; in led_7seg_init()
141 gpio_hog_list(phy_reset, ARRAY_SIZE(phy_reset), "atl,phy-reset", "reset-gpio", 0); in misc_init_r()
148 led_7seg_init(0xff); in misc_init_r()
150 return 0; in misc_init_r()
159 return 0; in checkboard()