Lines Matching +full:0 +full:x3150
17 #define PCH_TYPE_CPT 0x1c /* CougarPoint */
18 #define PCH_TYPE_PPT 0x1e /* IvyBridge */
21 #define PCH_STEP_A0 0
27 #define DEFAULT_GPIOBASE 0x0480
28 #define DEFAULT_PMBASE 0x0500
30 #define SMBUS_IO_BASE 0x0400
32 #define MAINBOARD_POWER_OFF 0
37 #define PSTS 0x06
38 #define SMLT 0x1b
39 #define SECSTS 0x1e
40 #define INTR 0x3c
41 #define BCTRL 0x3e
44 #define PERE (1 << 0)
46 #define PCH_EHCI1_DEV PCI_BDF(0, 0x1d, 0)
47 #define PCH_EHCI2_DEV PCI_BDF(0, 0x1a, 0)
48 #define PCH_XHCI_DEV PCI_BDF(0, 0x14, 0)
49 #define PCH_ME_DEV PCI_BDF(0, 0x16, 0)
52 #define PCH_DEV PCI_BDF(0, 0, 0)
53 #define PCH_VIDEO_DEV PCI_BDF(0, 2, 0)
56 #define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
57 #define SERIRQ_CNTL 0x64
59 #define GEN_PMCON_1 0xa0
60 #define GEN_PMCON_2 0xa2
61 #define GEN_PMCON_3 0xa4
62 #define ETR3 0xac
69 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
71 #define BIOS_CNTL 0xDC
72 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
73 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
74 #define GPIO_ROUT 0xb8
76 #define PIRQA_ROUT 0x60
77 #define PIRQB_ROUT 0x61
78 #define PIRQC_ROUT 0x62
79 #define PIRQD_ROUT 0x63
80 #define PIRQE_ROUT 0x68
81 #define PIRQF_ROUT 0x69
82 #define PIRQG_ROUT 0x6A
83 #define PIRQH_ROUT 0x6B
85 #define GEN_PMCON_1 0xa0
86 #define GEN_PMCON_2 0xa2
87 #define GEN_PMCON_3 0xa4
88 #define ETR3 0xac
92 #define PMBASE 0x40
93 #define ACPI_CNTL 0x44
94 #define BIOS_CNTL 0xDC
95 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
96 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
97 #define GPIO_ROUT 0xb8
100 #define PCH_IDE_DEV PCI_BDF(0, 0x1f, 1)
101 #define PCH_SATA_DEV PCI_BDF(0, 0x1f, 2)
102 #define PCH_SATA2_DEV PCI_BDF(0, 0x1f, 5)
104 #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */
108 #define IDE_PSDE0 (1 << 0)
110 #define IDE_SDMA_TIM 0x4a
112 #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
113 #define SIG_MODE_SEC_NORMAL (0 << 18)
116 #define SIG_MODE_PRI_NORMAL (0 << 16)
126 #define PCB0 (1 << 0)
128 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
129 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
130 #define SATA_SP 0xd0 /* Scratchpad */
133 #define SATA_IOBP_SP0G3IR 0xea000151
134 #define SATA_IOBP_SP1G3IR 0xea000051
136 #define VCH 0x0000 /* 32bit */
137 #define VCAP1 0x0004 /* 32bit */
138 #define VCAP2 0x0008 /* 32bit */
139 #define PVC 0x000c /* 16bit */
140 #define PVS 0x000e /* 16bit */
142 #define V0CAP 0x0010 /* 32bit */
143 #define V0CTL 0x0014 /* 32bit */
144 #define V0STS 0x001a /* 16bit */
146 #define V1CAP 0x001c /* 32bit */
147 #define V1CTL 0x0020 /* 32bit */
148 #define V1STS 0x0026 /* 16bit */
150 #define RCTCL 0x0100 /* 32bit */
151 #define ESD 0x0104 /* 32bit */
152 #define ULD 0x0110 /* 32bit */
153 #define ULBA 0x0118 /* 64bit */
155 #define RP1D 0x0120 /* 32bit */
156 #define RP1BA 0x0128 /* 64bit */
157 #define RP2D 0x0130 /* 32bit */
158 #define RP2BA 0x0138 /* 64bit */
159 #define RP3D 0x0140 /* 32bit */
160 #define RP3BA 0x0148 /* 64bit */
161 #define RP4D 0x0150 /* 32bit */
162 #define RP4BA 0x0158 /* 64bit */
163 #define HDD 0x0160 /* 32bit */
164 #define HDBA 0x0168 /* 64bit */
165 #define RP5D 0x0170 /* 32bit */
166 #define RP5BA 0x0178 /* 64bit */
167 #define RP6D 0x0180 /* 32bit */
168 #define RP6BA 0x0188 /* 64bit */
170 #define RPC 0x0400 /* 32bit */
171 #define RPFN 0x0404 /* 32bit */
173 #define TRSR 0x1e00 /* 8bit */
174 #define TRCR 0x1e10 /* 64bit */
175 #define TWDR 0x1e18 /* 64bit */
177 #define IOTR0 0x1e80 /* 64bit */
178 #define IOTR1 0x1e88 /* 64bit */
179 #define IOTR2 0x1e90 /* 64bit */
180 #define IOTR3 0x1e98 /* 64bit */
182 #define TCTL 0x3000 /* 8bit */
184 #define NOINT 0
193 #define DIR_IAR 0 /* Interrupt A Pin Offset */
195 #define PIRQA 0
205 #define IOBPIRI 0x2330
206 #define IOBPD 0x2334
207 #define IOBPS 0x2338
212 #define D31IP 0x3100 /* 32bit */
217 #define D30IP 0x3104 /* 32bit */
218 #define D30IP_PIP 0 /* PCI Bridge Pin */
219 #define D29IP 0x3108 /* 32bit */
220 #define D29IP_E1P 0 /* EHCI #1 Pin */
221 #define D28IP 0x310c /* 32bit */
229 #define D28IP_P1IP 0 /* PCI Express Port 1 */
230 #define D27IP 0x3110 /* 32bit */
231 #define D27IP_ZIP 0 /* HD Audio Pin */
232 #define D26IP 0x3114 /* 32bit */
233 #define D26IP_E2P 0 /* EHCI #2 Pin */
234 #define D25IP 0x3118 /* 32bit */
235 #define D25IP_LIP 0 /* GbE LAN Pin */
236 #define D22IP 0x3124 /* 32bit */
240 #define D22IP_MEI1IP 0 /* MEI #1 Pin */
241 #define D20IP 0x3128 /* 32bit */
242 #define D20IP_XHCIIP 0
243 #define D31IR 0x3140 /* 16bit */
244 #define D30IR 0x3142 /* 16bit */
245 #define D29IR 0x3144 /* 16bit */
246 #define D28IR 0x3146 /* 16bit */
247 #define D27IR 0x3148 /* 16bit */
248 #define D26IR 0x314c /* 16bit */
249 #define D25IR 0x3150 /* 16bit */
250 #define D22IR 0x315c /* 16bit */
251 #define D20IR 0x3160 /* 16bit */
252 #define OIC 0x31fe /* 16bit */
254 #define SPI_FREQ_SWSEQ 0x3893
255 #define SPI_DESC_COMP0 0x38b0
256 #define SPI_FREQ_WR_ERA 0x38b4
262 #define HPTC 0x3404 /* 32bit */
263 #define BUC 0x3414 /* 32bit */
265 #define FD 0x3418 /* 32bit */
266 #define DISPBDF 0x3424 /* 16bit */
267 #define FD2 0x3428 /* 32bit */
268 #define CG 0x341c /* 32bit */
270 /* Function Disable 1 RCBA 0x3418 */
271 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26))
284 /* Function Disable 2 RCBA 0x3428 */
289 #define PCH_ENABLE_DBDF (1 << 0)
292 #define GPIO_USE_SEL 0x00
293 #define GP_IO_SEL 0x04
294 #define GP_LVL 0x0c
295 #define GPO_BLINK 0x18
296 #define GPI_INV 0x2c
297 #define GPIO_USE_SEL2 0x30
298 #define GP_IO_SEL2 0x34
299 #define GP_LVL2 0x38
300 #define GPIO_USE_SEL3 0x40
301 #define GP_IO_SEL3 0x44
302 #define GP_LVL3 0x48
303 #define GP_RST_SEL1 0x60
304 #define GP_RST_SEL2 0x64
305 #define GP_RST_SEL3 0x68
308 #define PM1_STS 0x00
316 #define TMROF_STS (1 << 0)
317 #define PM1_EN 0x02
322 #define TMROF_EN (1 << 0)
323 #define PM1_CNT 0x04
326 #define SLP_TYP_S0 0
333 #define SCI_EN (1 << 0)
334 #define PM1_TMR 0x08
335 #define PROC_CNT 0x10
336 #define LV2 0x14
337 #define LV3 0x15
338 #define LV4 0x16
339 #define PM2_CNT 0x50 /* mobile only */
340 #define GPE0_STS 0x20
350 #define GPE0_EN 0x28
354 #define SMI_EN 0x30
367 #define GBL_SMI_EN (1 << 0) /* SMI# generation at all? */
368 #define SMI_STS 0x34
369 #define ALT_GP_SMI_EN 0x38
370 #define ALT_GP_SMI_STS 0x3a
371 #define GPE_CNTL 0x42
372 #define DEVACT_STS 0x44
373 #define SS_CNT 0x50
374 #define C3_RES 0x54
375 #define TCO1_STS 0x64
377 #define TCO2_STS 0x66