x86/dts/crownbay.dts

1 // SPDX-License-Identifier: GPL-2.0+
6 /dts-v1/;
8 #include <dt-bindings/interrupt-router/intel-irq.h>
31 		#address-cells = <1>;
32 		#size-cells = <0>;
34 		cpu@0 {
35 			device_type = "cpu";
36 			compatible = "cpu-x86";
38 			intel,apic-id = <0>;
41 		cpu@1 {
42 			device_type = "cpu";
43 			compatible = "cpu-x86";
45 			intel,apic-id = <1>;
53 		 * U-Boot serial console. If we want to use UART from Topcliff
56 		 * For example, stdout-path = &pciuart0 will use the first
59 		stdout-path = "/serial";
69 		#address-cells = <3>;
70 		#size-cells = <2>;
71 		compatible = "pci-x86";
72 		u-boot,dm-pre-reloc;
78 			#address-cells = <3>;
79 			#size-cells = <2>;
80 			compatible = "pci-bridge";
81 			u-boot,dm-pre-reloc;
85 				#address-cells = <3>;
86 				#size-cells = <2>;
87 				compatible = "pci-bridge";
88 				u-boot,dm-pre-reloc;
97 					u-boot,dm-pre-reloc;
100 					reg-shift = <0>;
101 					clock-frequency = <1843200>;
102 					current-speed = <115200>;
111 					u-boot,dm-pre-reloc;
114 					reg-shift = <0>;
115 					clock-frequency = <1843200>;
116 					current-speed = <115200>;
125 					u-boot,dm-pre-reloc;
128 					reg-shift = <0>;
129 					clock-frequency = <1843200>;
130 					current-speed = <115200>;
139 					u-boot,dm-pre-reloc;
142 					reg-shift = <0>;
143 					clock-frequency = <1843200>;
144 					current-speed = <115200>;
152 			#address-cells = <1>;
153 			#size-cells = <1>;
155 			irq-router {
156 				compatible = "intel,irq-router";
157 				intel,pirq-config = "pci";
158 				intel,actl-addr = <0x58>;
159 				intel,pirq-link = <0x60 8>;
160 				intel,pirq-mask = <0xcee0>;
161 				intel,pirq-routing = <
167 					PCI_BDF(0, 23, 0) INTC PIRQC
171 					PCI_BDF(0, 24, 0) INTC PIRQD
175 					PCI_BDF(0, 25, 0) INTC PIRQA
179 					PCI_BDF(0, 26, 0) INTC PIRQB
189 					* devices per U-Boot current PCI bus
200 					PCI_BDF(2, 4, 0) INTC PIRQC
201 					PCI_BDF(2, 4, 1) INTC PIRQC
212 					PCI_BDF(2, 12, 0) INTC PIRQC
213 					PCI_BDF(2, 12, 1) INTC PIRQC
214 					PCI_BDF(2, 12, 2) INTC PIRQC
215 					PCI_BDF(2, 12, 3) INTC PIRQC
216 					PCI_BDF(2, 12, 4) INTC PIRQC
221 				#address-cells = <1>;
222 				#size-cells = <0>;
223 				compatible = "intel,ich7-spi";
224 				spi-flash@0 {
227 						"spi-flash";
228 					memory-map = <0xffe00000 0x00200000>;
233 				compatible = "intel,ich6-gpio";
234 				u-boot,dm-pre-reloc;
236 				bank-name = "A";
240 				compatible = "intel,ich6-gpio";
241 				u-boot,dm-pre-reloc;
243 				bank-name = "B";