1 // SPDX-License-Identifier: GPL-2.0+
46 	mask = ~(CONFIG_SYS_MONITOR_LEN - 1);  in quark_setup_mtrr()
54 	mask = ~(ESRAM_SIZE - 1);  in quark_setup_mtrr()
70 	/* GPIO - D31:F0:R44h */  in quark_setup_bars()
74 	/* ACPI PM1 Block - D31:F0:R48h */  in quark_setup_bars()
78 	/* GPE0 - D31:F0:R4Ch */  in quark_setup_bars()
82 	/* WDT - D31:F0:R84h */  in quark_setup_bars()
86 	/* RCBA - D31:F0:RF0h */  in quark_setup_bars()
90 	/* ACPI P Block - Msg Port 04:R70h */  in quark_setup_bars()
94 	/* SPI DMA - Msg Port 04:R7Ah */  in quark_setup_bars()
111 	 * Call the board-specific codes to perform this task.  in quark_pcie_early_init()
131 	/* Step5: De-assert PERST# */  in quark_pcie_early_init()
154 				(1 << 8) | (1 << 9), (1 << 7) | (1 << 10));  in quark_usb_early_init()
176 				(1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |  in quark_thermal_early_init()
177 				(1 << 12), 1 << 9);  in quark_thermal_early_init()
184 				(1 << 8) | (1 << 9), 1 << 8);  in quark_thermal_early_init()
229 	 * Quark SoC has some non-standard BARs (excluding PCI standard BARs)  in arch_cpu_init()
240 	/* Turn on legacy segments (A/B/E/F) decode to system RAM */  in arch_cpu_init()
251 	 * Quark SoC holds the PCIe controller in reset following a power on.  in arch_cpu_init_dm()
252 	 * U-Boot needs to release the PCIe controller from reset. The PCIe  in arch_cpu_init_dm()
253 	 * controller (D23:F0/F1) will not be visible in PCI configuration  in arch_cpu_init_dm()
277 	/* PCIe upstream non-posted & posted request size */  in quark_pcie_init()
326 	writew(PIRQC, &rcba->rmu_ir);  in quark_irq_init()
328 	       &rcba->d23_ir);  in quark_irq_init()
329 	writew(PIRQD, &rcba->core_ir);  in quark_irq_init()
331 	       &rcba->d20d21_ir);  in quark_irq_init()
350 	 * is not saved successfully, it is not a severe error that will  in arch_misc_init()
356 	/* Assign a unique I/O APIC ID */  in arch_misc_init()
372 	val = readl(&rcba->esd);  in board_final_cleanup()
374 	writel(val, &rcba->esd);  in board_final_cleanup()