Lines Matching refs:lo
112 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_freq()
116 perf_ctl.lo = msr.lo & 0xff00; in set_max_freq()
123 ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); in set_max_freq()
278 msr.lo &= ~0xff000000; in initialize_vr_config()
281 msr.lo |= (min_vid & 0xff) << 24; in initialize_vr_config()
286 msr.lo &= ~0xffff; in initialize_vr_config()
292 msr.lo |= 0x006a; /* 1.56V */ in initialize_vr_config()
294 msr.lo |= 0x006f; /* 1.60V */ in initialize_vr_config()
416 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_ratio()
420 perf_ctl.lo = (msr.lo & 0xff) << 8; in set_max_ratio()
424 perf_ctl.lo = msr.lo & 0xff00; in set_max_ratio()
429 ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); in set_max_ratio()
441 num_threads = (msr.lo >> 0) & 0xffff; in broadwell_init()
442 num_cores = (msr.lo >> 16) & 0xffff; in broadwell_init()
465 num_banks = msr.lo & 0xff; in configure_mca()
466 msr.lo = 0; in configure_mca()
482 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */ in enable_lapic_tpr()
492 msr.lo |= (1 << 31); /* Timed MWAIT Enable */ in configure_c_states()
493 msr.lo |= (1 << 30); /* Package c-state Undemotion Enable */ in configure_c_states()
494 msr.lo |= (1 << 29); /* Package c-state Demotion Enable */ in configure_c_states()
495 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */ in configure_c_states()
496 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */ in configure_c_states()
497 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */ in configure_c_states()
498 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */ in configure_c_states()
499 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */ in configure_c_states()
504 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */ in configure_c_states()
508 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */ in configure_c_states()
509 msr.lo |= (1 << 1); /* C1E Enable */ in configure_c_states()
510 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */ in configure_c_states()
515 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; in configure_c_states()
520 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; in configure_c_states()
525 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; in configure_c_states()
530 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_3_LIMIT; in configure_c_states()
535 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_4_LIMIT; in configure_c_states()
540 msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_5_LIMIT; in configure_c_states()
549 msr.lo |= (1 << 0); /* Fast String enable */ in configure_misc()
550 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ in configure_misc()
551 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ in configure_misc()
555 msr.lo = 0; in configure_misc()
560 msr.lo = 1 << 4; in configure_misc()
575 if ((msr.lo & (1 << 30)) && tcc_offset) { in configure_thermal_target()
577 msr.lo &= ~(0xf << 24); /* Bits 27:24 */ in configure_thermal_target()
578 msr.lo |= (tcc_offset & 0xf) << 24; in configure_thermal_target()
592 msr.lo |= 1; in configure_dca_cap()
609 msr.lo &= ~0xf; in set_energy_perf_bias()
610 msr.lo |= policy & 0xf; in set_energy_perf_bias()
660 if (!(msr.lo & PLATFORM_INFO_SET_TDP)) in cpu_set_power_limits()
665 power_unit = 2 << ((msr.lo & 0xf) - 1); in cpu_set_power_limits()
669 tdp = msr.lo & 0x7fff; in cpu_set_power_limits()
670 min_power = (msr.lo >> 16) & 0x7fff; in cpu_set_power_limits()
688 limit.lo = 0; in cpu_set_power_limits()
689 limit.lo |= tdp & PKG_POWER_LIMIT_MASK; in cpu_set_power_limits()
690 limit.lo |= PKG_POWER_LIMIT_EN; in cpu_set_power_limits()
691 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << in cpu_set_power_limits()
703 writel(limit.lo, MCHBAR_REG(MCH_PKG_POWER_LIMIT_LO)); in cpu_set_power_limits()
707 msr.lo = readl(MCHBAR_REG(MCH_DDR_POWER_LIMIT_LO)); in cpu_set_power_limits()
715 limit.lo = msr.lo & 0xff; in cpu_set_power_limits()
725 info->cpu_freq = ((msr.lo >> 8) & 0xff) * BROADWELL_BCLK * 1000000; in broadwell_get_info()