cpu/baytrail/cpu.c

1 // SPDX-License-Identifier: GPL-2.0+
42  * Configure the internal clock of both SIO HS-UARTs, if they are enabled
52 	/* Loop over the 2 HS-UARTs */  in arch_cpu_init_dm()
70 	/* Enable speed step */  in set_max_freq()
88 	perf_ctl.hi = 0;  in set_max_freq()
100 	 * On BayTrail the turbo disable bit is actually scoped at the  in cpu_x86_baytrail_probe()
101 	 * building-block level, not package. For non-BSP cores that are  in cpu_x86_baytrail_probe()
111 	/* Disable C1E */  in cpu_x86_baytrail_probe()
153 	info->cpu_freq = tsc_freq();  in baytrail_get_info()
154 	info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;  in baytrail_get_info()
164 	 * Use the algorithm described in Intel 64 and IA-32 Architectures  in baytrail_get_count()
166 	 * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping  in baytrail_get_count()
195 	{ .compatible = "intel,baytrail-cpu" },