riscv/dts/ae350_32.dts

1 /dts-v1/;
4 	#address-cells = <1>;
5 	#size-cells = <1>;
16 		stdout-path = "uart0:38400n8";
20 		#address-cells = <1>;
21 		#size-cells = <0>;
22 		timebase-frequency = <60000000>;
29 			mmu-type = "riscv,sv32";
30 			clock-frequency = <60000000>;
31 			d-cache-size = <0x8000>;
32 			d-cache-line-size = <32>;
33 			CPU0_intc: interrupt-controller {
34 				#interrupt-cells = <1>;
35 				interrupt-controller;
36 				compatible = "riscv,cpu-intc";
47 		#address-cells = <1>;
48 		#size-cells = <1>;
49 		compatible = "andestech,riscv-ae350-soc";
52 	plic0: interrupt-controller@e4000000 {
54 		#address-cells = <1>;
55 		#interrupt-cells = <1>;
56 		interrupt-controller;
59 		interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
62 	plic1: interrupt-controller@e6400000 {
64 		#address-cells = <1>;
65 		#interrupt-cells = <1>;
66 		interrupt-controller;
69 		interrupts-extended = <&CPU0_intc 3>;
74 			interrupts-extended = <&CPU0_intc 7>;
80 		#clock-cells = <0>;
81 		compatible = "fixed-clock";
82 		clock-frequency = <100000000>;
88 		clock-frequency = <60000000>;
89 		interrupts = <3 4>;
90 		interrupt-parent = <&plic0>;
96 		interrupts = <9 4>;
97 		clock-frequency = <19660800>;
98 		reg-shift = <2>;
99 		reg-offset = <32>;
100 		no-loopback-test = <1>;
101 		interrupt-parent = <&plic0>;
107 		interrupts = <19 4>;
108 		interrupt-parent = <&plic0>;
113 		max-frequency = <100000000>;
114 		clock-freq-min-max = <400000 100000000>;
115 		fifo-depth = <0x10>;
117 		interrupts = <18 4>;
118 		cap-sd-highspeed;
119 		interrupt-parent = <&plic0>;
125 		interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
126 		dma-channels = <8>;
127 		interrupt-parent = <&plic0>;
133 		interrupts = <20 4>;
134 		interrupt-parent = <&plic0>;
145 		interrupts = <17 4>;
146 		interrupt-parent = <&plic0>;
150 		interrupts = <0x17 0x4>;
151 		interrupt-parent = <0x2>;
157 		interrupts = <0x16 0x4>;
158 		interrupt-parent = <0x2>;
164 		interrupts = <0x15 0x4>;
165 		interrupt-parent = <0x2>;
171 		interrupts = <0x14 0x4>;
172 		interrupt-parent = <0x2>;
178 		interrupts = <0x13 0x4>;
179 		interrupt-parent = <0x2>;
185 		interrupts = <0x12 0x4>;
186 		interrupt-parent = <0x2>;
192 		interrupts = <0x11 0x4>;
193 		interrupt-parent = <0x2>;
199 		interrupts = <0x10 0x4>;
200 		interrupt-parent = <0x2>;
206 		compatible = "cfi-flash";
208 		bank-width = <2>;
209 		device-width = <1>;
215 		#address-cells = <1>;
216 		#size-cells = <0>;
217 		num-cs = <1>;
219 		interrupts = <4 4>;
220 		interrupt-parent = <&plic0>;
222 			compatible = "spi-flash";
223 			spi-max-frequency = <50000000>;
225 			spi-cpol;
226 			spi-cpha;