include/asm/processor.h

19 #define MSR_UCLE	(1<<26)		/* User-mode cache lock enable (e500) */
40 #define MSR_IS		(1<<5)		/* Book E Instruction space */
42 #define MSR_DS		(1<<4)		/* Book E Data space */
67 #define FPSCR_ZX	0x04000000	/* Zero-devide exception summary */
70 #define FPSCR_VXISI	0x00800000	/* Invalid op for Inv - Inv */
87 #define FPSCR_NI	0x00000004	/* FPU non IEEE-Mode */
103 #define SPRN_DAC1	0x13C	/* Book E Data Address Compare 1 */
104 #define SPRN_DAC2	0x13D	/* Book E Data Address Compare 2 */
159 #define SPRN_DBCR0	0x134		/* Book E Debug Control Register 0 */
165 #define SPRN_DBCR1	0x135		/* Book E Debug Control Register 1 */
169 #define SPRN_DBSR	0x130		/* Book E Debug Status Register */
170 #define   DBSR_IC	    0x08000000	/* Book E Instruction Completion  */
171 #define   DBSR_TIE	    0x01000000	/* Book E Trap Instruction Event */
181 #define SPRN_DCWR	0x3BA	/* Data Cache Write-thru Register */
182 #define   DCWR_COPY		0	/* Copy-back */
183 #define   DCWR_WRITE		1	/* Write-through */
187 #define SPRN_DEAR	0x03D	/* Book E Data Error Address Register */
209 #define SPRN_ESR	0x03E		/* Book E Exception Syndrome Register */
211 #define   ESR_IMCP	0x80000000	/* Instr. Machine Check - Protection */
212 #define   ESR_IMCN	0x40000000	/* Instr. Machine Check - Non-config */
213 #define   ESR_IMCB	0x20000000	/* Instr. Machine Check - Bus error */
214 #define   ESR_IMCT	0x10000000	/* Instr. Machine Check - Timeout */
215 #define   ESR_PIL	0x08000000	/* Program Exception - Illegal */
216 #define   ESR_PPR	0x04000000	/* Program Exception - Priveleged */
217 #define   ESR_PTR	0x02000000	/* Program Exception - Trap */
218 #define   ESR_DST	0x00800000	/* Storage Exception - Data miss */
219 #define   ESR_DIZ	0x00400000	/* Storage Exception - Zone fault */
249 #define   HID0_ENMAS7	(1<<7)		/* Enable MAS7 Update for 36-bit phys */
267 #define SPRN_IAC1	0x138	/* Book E Instruction Address Compare 1 */
268 #define SPRN_IAC2	0x139	/* Book E Instruction Address Compare 2 */
326 #define SPRN_PID	0x030	/* Book E Process ID */
327 #define SPRN_PIR	0x11E	/* Book E Processor Identification Register */
364 #define SPRN_TBHU	0x3CC	/* Time Base High User-mode */
366 #define SPRN_TBLU	0x3CD	/* Time Base Low User-mode */
374 #define SPRN_TCR	0x154	/* Book E Timer Control Register */
377 #define  TCR_WP(x)		(((64-x)&0x3)<<30)| \
378 				(((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
414 #define SPRN_TSR	0x150	/* Book E Timer Status Register */
435 /* Book E definitions */
487 #define   L1CSR0_CUL		0x00000400	/* (D-)Cache Unable to Lock */
488 #define   L1CSR0_DCLFR		0x00000100	/* D-Cache Lock Flash Reset */
493 #define   L1CSR1_ICUL		0x00000400	/* I-Cache Unable to Lock */
494 #define   L1CSR1_ICLFR		0x00000100	/* I-Cache Lock Flash Reset */
570 #define MCSR_ICP	0x04000000	/* I-Cache Parity Error */
571 #define MCSR_DCSP	0x02000000	/* D-Cache Search Parity Error */
572 #define MCSR_DCFP	0x01000000	/* D-Cache Flush Parity Error */
591 /* Short-hand versions for a number of the above SPRNs */
659 #define SVR	SPRN_SVR	/* System-On-Chip Version Register */
767 #define   BESR_DSES	0x80000000	/* Data-Side Error Status */
839 /* System-On-Chip Version Register */
841 /* System-On-Chip Version Register (SVR) field extraction */
862  * AMCC has further subdivided the standard PowerPC 16-bit version and
1023 #define SVR_SUBVER(svr)	(((svr) >>  8) & 0xFF)	/* Process/MFG sub-version */
1036 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
1038 /* whether MPC8xxxE (i.e. has SEC) */
1197 	  .mask = (1 << (nc)) - 1 }
1234 /* Lazy FPU handling on uni-processor */
1242  * to match the mac we can raise this. -- Cort
1260 	void		*pgdir;		/* root of page-table tree */
1277 	(struct pt_regs *)INIT_SP - 1, /* regs */ \
1297 	return (t->regs) ? t->regs->nip : 0;  in thread_saved_pc()
1306 #define KSTK_EIP(tsk)  ((tsk)->thread.regs->nip)
1307 #define KSTK_ESP(tsk)  ((tsk)->thread.regs->gpr[1])
1318 /* in process.c - for early bootup debug -- Cort */