Lines Matching +full:0 +full:xc4000000
101 u32 temp = 0; in fsl_erratum_a006261_workaround()
140 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { in config_qe_ioports()
156 for (portnum = 0; portnum < 4; portnum++) { in config_8560_ioports()
157 uint pmsk = 0, in config_8560_ioports()
158 ppar = 0, in config_8560_ioports()
159 psor = 0, in config_8560_ioports()
160 pdir = 0, in config_8560_ioports()
161 podr = 0, in config_8560_ioports()
162 pdat = 0; in config_8560_ioports()
163 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; in config_8560_ioports()
169 * index 0 refers to pin 31, in config_8560_ioports()
170 * index 31 refers to pin 0 in config_8560_ioports()
191 if (pmsk != 0) { in config_8560_ioports()
223 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { in disable_cpc_sram()
235 out_be32(&cpc->cpccsr0, 0); in disable_cpc_sram()
236 out_be32(&cpc->cpcsrcr0, 0); in disable_cpc_sram()
249 char buffer[HWCONFIG_BUFFER_SIZE] = {0}; in enable_tdm_law()
250 int tdm_hwconfig_enabled = 0; in enable_tdm_law()
258 if (ret > 0) { in enable_tdm_law()
272 u32 size = 0; in enable_cpc()
277 int cpc_args = 0; in enable_cpc()
282 if (ret > 0) { in enable_cpc()
293 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { in enable_cpc()
297 if (cpc_args == 0) in enable_cpc()
334 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { in invalidate_cpc()
376 u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); in fsl_erratum_a007212_workaround()
377 u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); in fsl_erratum_a007212_workaround()
378 u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80); in fsl_erratum_a007212_workaround()
380 u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40); in fsl_erratum_a007212_workaround()
381 u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48); in fsl_erratum_a007212_workaround()
383 u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60); in fsl_erratum_a007212_workaround()
384 u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); in fsl_erratum_a007212_workaround()
393 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> in fsl_erratum_a007212_workaround()
396 /* check if RCW sets ratio to 0, required by this workaround */ in fsl_erratum_a007212_workaround()
397 if (ddr_pll_ratio != 0) in fsl_erratum_a007212_workaround()
399 ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >> in fsl_erratum_a007212_workaround()
403 if (ddr_pll_ratio == 0) { in fsl_erratum_a007212_workaround()
409 setbits_be32(plldadcr1, 0x02000001); in fsl_erratum_a007212_workaround()
411 setbits_be32(plldadcr2, 0x02000001); in fsl_erratum_a007212_workaround()
413 setbits_be32(plldadcr3, 0x02000001); in fsl_erratum_a007212_workaround()
416 setbits_be32(dpdovrcr4, 0xe0000000); in fsl_erratum_a007212_workaround()
417 out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1)); in fsl_erratum_a007212_workaround()
419 out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1)); in fsl_erratum_a007212_workaround()
421 out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1)); in fsl_erratum_a007212_workaround()
425 clrbits_be32(plldadcr1, 0x02000001); in fsl_erratum_a007212_workaround()
427 clrbits_be32(plldadcr2, 0x02000001); in fsl_erratum_a007212_workaround()
429 clrbits_be32(plldadcr3, 0x02000001); in fsl_erratum_a007212_workaround()
432 clrbits_be32(dpdovrcr4, 0xe0000000); in fsl_erratum_a007212_workaround()
455 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) in cpu_init_f()
509 return 0; in cpu_init_f()
522 int i = 0; in enable_cluster_l2()
532 return 0; in enable_cluster_l2()
536 return 0; in enable_cluster_l2()
543 int j, cluster_valid = 0; in enable_cluster_l2()
545 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); in enable_cluster_l2()
550 for (j = 0; j < 4; j++) { in enable_cluster_l2()
561 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); in enable_cluster_l2()
567 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) in enable_cluster_l2()
574 return 0; in enable_cluster_l2()
605 out_be32(&l2cache->l2srbar0, 0x0); in l2cache_init()
606 out_be32(&l2cache->l2srbar1, 0x0); in l2cache_init()
608 /* set MBECCDIS=0, SBECCDIS=0 */ in l2cache_init()
613 /* set L2E=0, L2SRAM=0 */ in l2cache_init()
620 l2siz_field = (cache_ctl >> 28) & 0x3; in l2cache_init()
623 case 0x0: in l2cache_init()
624 printf(" unknown size (0x%08x)\n", cache_ctl); in l2cache_init()
627 case 0x1: in l2cache_init()
632 cache_ctl = 0xc4000000; in l2cache_init()
635 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ in l2cache_init()
638 case 0x2: in l2cache_init()
643 cache_ctl = 0xc8000000; in l2cache_init()
646 /* set L2E=1, L2I=1, & L2SRAM=0 */ in l2cache_init()
647 cache_ctl = 0xc0000000; in l2cache_init()
650 case 0x3: in l2cache_init()
652 /* set L2E=1, L2I=1, & L2SRAM=0 */ in l2cache_init()
653 cache_ctl = 0xc0000000; in l2cache_init()
665 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); in l2cache_init()
699 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); in l2cache_init()
705 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, in l2cache_init()
713 return 0; in l2cache_init()
756 if (n > 0) in cpu_init_r()
760 if (res > 0) { in cpu_init_r()
761 enable_cpu_a011_workaround = 0; in cpu_init_r()
791 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); in cpu_init_r()
797 spin_table_compat = 0; in cpu_init_r()
824 #define MCFGR_AXIPIPE 0x000000f0 in cpu_init_r()
825 if (IS_SVR_REV(svr, 1, 0)) in cpu_init_r()
830 if (IS_SVR_REV(svr, 1, 0)) { in cpu_init_r()
832 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; in cpu_init_r()
834 for (i = 0; i < 12; i++) { in cpu_init_r()
835 p += i + (i > 5 ? 11 : 0); in cpu_init_r()
836 out_be32(p, 0x2); in cpu_init_r()
838 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; in cpu_init_r()
839 out_be32(p, 0x34); in cpu_init_r()
868 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; in cpu_init_r()
913 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal in cpu_init_r()
917 if (IS_SVR_REV(get_svr(), 1, 0)) { in cpu_init_r()
966 if (pamu_init() < 0) in cpu_init_r()
985 * For P1022/1013 Rev1.0 silicon, after power on SATA host in cpu_init_r()
991 if (IS_SVR_REV(svr, 1, 0) && in cpu_init_r()
1008 return 0; in cpu_init_r()
1038 uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */ in cpu_secondary_init_r()
1040 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ in cpu_secondary_init_r()
1056 return 0; in board_late_init()