Lines Matching +full:pex +full:- +full:l0 +full:- +full:rst
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
4 * Copyright (C) 2008-2009 MontaVista Software, Inc.
53 int bus = PCI_BUS(dev) - hose->first_busno; in mpc83xx_pcie_remap_cfg()
55 struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data; in mpc83xx_pcie_remap_cfg()
56 pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; in mpc83xx_pcie_remap_cfg() local
57 struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; in mpc83xx_pcie_remap_cfg()
61 if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK) in mpc83xx_pcie_remap_cfg()
62 return -1; in mpc83xx_pcie_remap_cfg()
65 * PCI-E controller does not check the device number bits and just in mpc83xx_pcie_remap_cfg()
69 return -1; in mpc83xx_pcie_remap_cfg()
71 out_le32(&out_win->tarl, dev_base); in mpc83xx_pcie_remap_cfg()
80 #define cfg_read_err(val) do { *val = -1; } while (0)
95 cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
115 * There are no spare BATs to remap all PCI-E windows for U-Boot, so in PCIE_OP()
117 * that's why we don't register PCI-E hoses by default. in PCIE_OP()
122 if (reg->size == 0) in PCIE_OP()
125 hose->regions[i] = *reg; in PCIE_OP()
126 hose->region_count++; in PCIE_OP()
129 i = hose->region_count++; in PCIE_OP()
130 hose->regions[i].bus_start = 0; in PCIE_OP()
131 hose->regions[i].phys_start = 0; in PCIE_OP()
132 hose->regions[i].size = gd->ram_size; in PCIE_OP()
133 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; in PCIE_OP()
135 i = hose->region_count++; in PCIE_OP()
136 hose->regions[i].bus_start = CONFIG_SYS_IMMR; in PCIE_OP()
137 hose->regions[i].phys_start = CONFIG_SYS_IMMR; in PCIE_OP()
138 hose->regions[i].size = 0x100000; in PCIE_OP()
139 hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY; in PCIE_OP()
141 hose->first_busno = pci_last_busno() + 1; in PCIE_OP()
142 hose->last_busno = 0xff; in PCIE_OP()
144 hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; in PCIE_OP()
146 hose->priv_data = &pcie_priv[bus]; in PCIE_OP()
157 hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK; in PCIE_OP()
167 hose->last_busno = pci_hose_scan(hose); in PCIE_OP()
180 pex83xx_t *pex = &immr->pciexp[bus]; in mpc83xx_pcie_init_bus() local
190 /* Enable pex csb bridge inbound & outbound transactions */ in mpc83xx_pcie_init_bus()
191 out_le32(&pex->bridge.pex_csb_ctrl, in mpc83xx_pcie_init_bus()
192 in_le32(&pex->bridge.pex_csb_ctrl) | PEX_CSB_CTRL_OBPIOE | in mpc83xx_pcie_init_bus()
196 out_le32(&pex->bridge.pex_csb_obctrl, PEX_CSB_OBCTRL_PIOE | in mpc83xx_pcie_init_bus()
200 out_win = &pex->bridge.pex_outbound_win[0]; in mpc83xx_pcie_init_bus()
201 out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | in mpc83xx_pcie_init_bus()
203 out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base); in mpc83xx_pcie_init_bus()
204 out_le32(&out_win->tarl, 0); in mpc83xx_pcie_init_bus()
205 out_le32(&out_win->tarh, 0); in mpc83xx_pcie_init_bus()
213 out_win = &pex->bridge.pex_outbound_win[i + 1]; in mpc83xx_pcie_init_bus()
214 out_le32(&out_win->bar, reg[i].phys_start); in mpc83xx_pcie_init_bus()
215 out_le32(&out_win->tarl, reg[i].bus_start); in mpc83xx_pcie_init_bus()
216 out_le32(&out_win->tarh, 0); in mpc83xx_pcie_init_bus()
222 out_le32(&out_win->ar, ar); in mpc83xx_pcie_init_bus()
225 out_le32(&pex->bridge.pex_csb_ibctrl, PEX_CSB_IBCTRL_PIOE); in mpc83xx_pcie_init_bus()
227 ram_sz = gd->ram_size; in mpc83xx_pcie_init_bus()
232 in_win = &pex->bridge.pex_inbound_win[i]; in mpc83xx_pcie_init_bus()
233 out_le32(&in_win->barl, barl); in mpc83xx_pcie_init_bus()
234 out_le32(&in_win->barh, 0x0); in mpc83xx_pcie_init_bus()
235 out_le32(&in_win->tar, tar); in mpc83xx_pcie_init_bus()
238 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | in mpc83xx_pcie_init_bus()
242 ram_sz -= 0x10000000; in mpc83xx_pcie_init_bus()
250 ram_sz -= 1; in mpc83xx_pcie_init_bus()
251 out_le32(&in_win->ar, PEX_IWAR_EN | PEX_IWAR_NSOV | in mpc83xx_pcie_init_bus()
258 in_win = &pex->bridge.pex_inbound_win[i]; in mpc83xx_pcie_init_bus()
259 out_le32(&in_win->barl, CONFIG_SYS_IMMR); in mpc83xx_pcie_init_bus()
260 out_le32(&in_win->barh, 0); in mpc83xx_pcie_init_bus()
261 out_le32(&in_win->tar, CONFIG_SYS_IMMR); in mpc83xx_pcie_init_bus()
262 out_le32(&in_win->ar, PEX_IWAR_EN | in mpc83xx_pcie_init_bus()
266 out_le32(&pex->bridge.pex_int_axi_misc_enb, in mpc83xx_pcie_init_bus()
267 in_le32(&pex->bridge.pex_int_axi_misc_enb) | 0x1E0); in mpc83xx_pcie_init_bus()
269 /* Hose configure header is memory-mapped */ in mpc83xx_pcie_init_bus()
270 hose_cfg_base = (void *)pex; in mpc83xx_pcie_init_bus()
275 (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk) in mpc83xx_pcie_init_bus()
293 * Clear non-reserved bits in status register. in mpc83xx_pcie_init_bus()
302 #define PCI_LTSSM_L0 0x16 /* L0 state */ in mpc83xx_pcie_init_bus()
321 * Release PCI RST Output signal. in mpc83xx_pcie_init()
322 * Power on to RST high must be at least 100 ms as per PCI spec. in mpc83xx_pcie_init()