Lines Matching +full:9 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Copyright (C) 2015-2016 Socionext Inc.
16 #define PHY_PIR_INIT BIT(0) /* Initialization Trigger */
17 #define PHY_PIR_ZCAL BIT(1) /* Impedance Calibration */
18 #define PHY_PIR_PLLINIT BIT(4) /* PLL Initialization */
19 #define PHY_PIR_DCAL BIT(5) /* DDL Calibration */
20 #define PHY_PIR_PHYRST BIT(6) /* PHY Reset */
21 #define PHY_PIR_DRAMRST BIT(7) /* DRAM Reset */
22 #define PHY_PIR_DRAMINIT BIT(8) /* DRAM Initialization */
23 #define PHY_PIR_WL BIT(9) /* Write Leveling */
24 #define PHY_PIR_QSGATE BIT(10) /* Read DQS Gate Training */
25 #define PHY_PIR_WLADJ BIT(11) /* Write Leveling Adjust */
26 #define PHY_PIR_RDDSKW BIT(12) /* Read Data Bit Deskew */
27 #define PHY_PIR_WRDSKW BIT(13) /* Write Data Bit Deskew */
28 #define PHY_PIR_RDEYE BIT(14) /* Read Data Eye Training */
29 #define PHY_PIR_WREYE BIT(15) /* Write Data Eye Training */
30 #define PHY_PIR_LOCKBYP BIT(28) /* PLL Lock Bypass */
31 #define PHY_PIR_DCALBYP BIT(29) /* DDL Calibration Bypass */
32 #define PHY_PIR_ZCALBYP BIT(30) /* Impedance Calib Bypass */
33 #define PHY_PIR_INITBYP BIT(31) /* Initialization Bypass */
36 #define PHY_PGCR1_INHVT BIT(26) /* VT Calculation Inhibit */
38 #define PHY_PGSR0_IDONE BIT(0) /* Initialization Done */
39 #define PHY_PGSR0_PLDONE BIT(1) /* PLL Lock Done */
40 #define PHY_PGSR0_DCDONE BIT(2) /* DDL Calibration Done */
41 #define PHY_PGSR0_ZCDONE BIT(3) /* Impedance Calibration Done */
42 #define PHY_PGSR0_DIDONE BIT(4) /* DRAM Initialization Done */
43 #define PHY_PGSR0_WLDONE BIT(5) /* Write Leveling Done */
44 #define PHY_PGSR0_QSGDONE BIT(6) /* DQS Gate Training Done */
45 #define PHY_PGSR0_WLADONE BIT(7) /* Write Leveling Adjust Done */
46 #define PHY_PGSR0_RDDONE BIT(8) /* Read Bit Deskew Done */
47 #define PHY_PGSR0_WDDONE BIT(9) /* Write Bit Deskew Done */
48 #define PHY_PGSR0_REDONE BIT(10) /* Read Eye Training Done */
49 #define PHY_PGSR0_WEDONE BIT(11) /* Write Eye Training Done */
50 #define PHY_PGSR0_DIERR BIT(20) /* DRAM Initialization Error */
51 #define PHY_PGSR0_WLERR BIT(21) /* Write Leveling Error */
52 #define PHY_PGSR0_QSGERR BIT(22) /* DQS Gate Training Error */
53 #define PHY_PGSR0_WLAERR BIT(23) /* Write Leveling Adj Error */
54 #define PHY_PGSR0_RDERR BIT(24) /* Read Bit Deskew Error */
55 #define PHY_PGSR0_WDERR BIT(25) /* Write Bit Deskew Error */
56 #define PHY_PGSR0_REERR BIT(26) /* Read Eye Training Error */
57 #define PHY_PGSR0_WEERR BIT(27) /* Write Eye Training Error */
61 #define PHY_PGSR1_VTSTOP BIT(30) /* VT Stop (v3-) */
80 #define PHY_DXCCR_DQSNRES_OPEN (0 << 9)
81 #define PHY_DXCCR_DQSNRES_688_OHM (1 << 9)
82 #define PHY_DXCCR_DQSNRES_611_OHM (2 << 9)
83 #define PHY_DXCCR_DQSNRES_550_OHM (3 << 9)
84 #define PHY_DXCCR_DQSNRES_500_OHM (4 << 9)
85 #define PHY_DXCCR_DQSNRES_458_OHM (5 << 9)
86 #define PHY_DXCCR_DQSNRES_393_OHM (6 << 9)
87 #define PHY_DXCCR_DQSNRES_344_OHM (7 << 9)
101 #define PHY_DTCR_DTMPR BIT(6) /* Data Training using MPR */