Lines Matching +full:clk +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
14 #include <asm/arch-tegra/clk_rst.h>
15 #include <asm/arch-tegra/timer.h>
20 * Clock types that we can use as a source. The Tegra30 has muxes for the
22 * source. This gives us a clock 'type' and exploits what commonality exists
47 CLOCK_TYPE_NONE = -1, /* invalid clock type */
51 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
55 * Clock source mux for each clock type. This just converts our enum into
59 * The extra column in each clock source array is used to store the mask
60 * bits in its register for the source.
62 #define CLK(x) CLOCK_ID_ ## x macro
64 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
65 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
67 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
68 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
70 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
71 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
73 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
74 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
76 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
89 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
91 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
92 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
94 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
100 * Clock type for each peripheral clock source. We put the name in each
141 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT), /* MIPI base-band HSI */
175 /* 0x38h */ /* Jumps to reg offset 0x3B0h - new for T30 */
220 * SPDIF - which is both 0x08 and 0x0c
223 #define NONE(name) (-1)
448 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_freq()
457 /* Returns a pointer to the clock source register for a peripheral */
466 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; in get_periph_source_reg()
470 assert(internal_id != -1); in get_periph_source_reg()
472 internal_id -= PERIPHC_VW_FIRST; in get_periph_source_reg()
473 return &clkrst->crc_clk_src_vw[internal_id]; in get_periph_source_reg()
475 return &clkrst->crc_clk_src[internal_id]; in get_periph_source_reg()
484 return -1; in get_periph_clock_info()
488 return -1; in get_periph_clock_info()
492 return -1; in get_periph_clock_info()
504 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) in get_periph_clock_id() argument
520 return clock_source[type][source]; in get_periph_clock_id()
524 * Given a peripheral ID and the required source clock, this returns which
525 * value should be programmed into the source mux for that peripheral.
527 * There is special code here to handle the one source type with 5 sources.
530 * @param source PLL id of required parent clock
533 * @return mux value (0-4, or -1 if not found)
551 return -1; in get_periph_clock_source()
558 u32 *clk; in clock_set_enable() local
564 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
566 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
567 reg = readl(clk); in clock_set_enable()
572 writel(reg, clk); in clock_set_enable()
585 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
587 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
695 } while (--timeout); in tegra_plle_train()
699 return -ETIMEDOUT; in tegra_plle_train()
771 } while (--timeout); in tegra_plle_enable()
775 return -ETIMEDOUT; in tegra_plle_enable()
818 { -1, },