Lines Matching +full:clk +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013-2015
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21 * Clock types that we can use as a source. The Tegra210 has muxes for the
23 * source. This gives us a clock 'type' and exploits what commonality exists
50 CLOCK_TYPE_PC2CC3M_T16, /* PC2CC3M_T, but w/16-bit divisor (I2C) */
59 CLOCK_TYPE_NONE = -1, /* invalid clock type */
63 CLOCK_MAX_MUX = 8 /* number of source options for each clock */
67 * Clock source mux for each clock type. This just converts our enum into
71 * The extra column in each clock source array is used to store the mask
72 * bits in its register for the source.
74 #define CLK(x) CLOCK_ID_ ## x macro
76 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC),
77 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
79 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO),
80 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
82 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
83 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
85 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE),
86 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
88 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC),
89 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
91 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC),
92 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
94 { CLK(AUDIO), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
95 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
97 { CLK(AUDIO), CLK(SFROM32KHZ), CLK(PERIPH), CLK(OSC),
98 CLK(EPCI), CLK(NONE), CLK(NONE), CLK(NONE),
100 { CLK(PERIPH), CLK(MEMORY), CLK(DISPLAY), CLK(AUDIO),
101 CLK(CGENERAL), CLK(DISPLAY2), CLK(OSC), CLK(NONE),
103 { CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
104 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
107 { CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
108 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
113 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
114 CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
117 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
118 CLK(SFROM32KHZ), CLK(NONE), CLK(OSC), CLK(NONE),
121 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
122 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
124 /* CLOCK_TYPE_PC2CC3M_T, w/16-bit divisor (I2C) */
125 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
126 CLK(MEMORY), CLK(NONE), CLK(OSC), CLK(NONE),
129 { CLK(MEMORY), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
130 CLK(PERIPH), CLK(NONE), CLK(AUDIO), CLK(NONE),
133 { CLK(MEMORY), CLK(NONE), CLK(NONE), CLK(NONE),
134 CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
137 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC),
138 CLK(MEMORY2), CLK(CGENERAL2), CLK(CGENERAL3), CLK(NONE),
141 { CLK(PERIPH), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
142 CLK(OSC), CLK(NONE), CLK(SFROM32KHZ), CLK(NONE),
145 { CLK(AUDIO), CLK(CGENERAL2), CLK(CGENERAL), CLK(CGENERAL3),
146 CLK(PERIPH), CLK(NONE), CLK(OSC), CLK(SRC2),
149 { CLK(PERIPH), CLK(CGENERAL_1), CLK(CGENERAL_0), CLK(NONE),
150 CLK(CGENERAL4_2), CLK(CGENERAL4_1), CLK(OSC), CLK(CGENERAL4_0),
155 * Clock type for each peripheral clock source. We put the name in each
350 * SPDIF - which is both 0x08 and 0x0c
353 #define NONE(name) (-1)
597 /* Y: 192 (192 - 223) */
679 reg = readl(&clkrst->crc_osc_ctrl); in clock_get_osc_freq()
698 /* Returns a pointer to the clock source register for a peripheral */
707 return &clkrst->crc_clk_src[PERIPH_ID_CSI+1]; in get_periph_source_reg()
711 assert(internal_id != -1); in get_periph_source_reg()
715 return &clkrst->crc_clk_src[internal_id]; in get_periph_source_reg()
719 internal_id -= PERIPHC_VW_FIRST; in get_periph_source_reg()
720 return &clkrst->crc_clk_src_vw[internal_id]; in get_periph_source_reg()
725 internal_id -= PERIPHC_X_FIRST; in get_periph_source_reg()
726 return &clkrst->crc_clk_src_x[internal_id]; in get_periph_source_reg()
730 internal_id -= PERIPHC_Y_FIRST; in get_periph_source_reg()
731 return &clkrst->crc_clk_src_y[internal_id]; in get_periph_source_reg()
740 return -1; in get_periph_clock_info()
744 return -1; in get_periph_clock_info()
748 return -1; in get_periph_clock_info()
760 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source) in get_periph_clock_id() argument
776 return clock_source[type][source]; in get_periph_clock_id()
780 * Given a peripheral ID and the required source clock, this returns which
781 * value should be programmed into the source mux for that peripheral.
783 * There is special code here to handle the one source type with 5 sources.
786 * @param source PLL id of required parent clock
789 * @return mux value (0-4, or -1 if not found)
807 return -1; in get_periph_clock_source()
814 u32 *clk; in clock_set_enable() local
820 clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)]; in clock_set_enable()
822 clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)]; in clock_set_enable()
824 clk = &clkrst->crc_clk_out_enb_x; in clock_set_enable()
826 clk = &clkrst->crc_clk_out_enb_y; in clock_set_enable()
828 reg = readl(clk); in clock_set_enable()
833 writel(reg, clk); in clock_set_enable()
846 reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)]; in reset_set_enable()
848 reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)]; in reset_set_enable()
850 reset = &clkrst->crc_rst_devices_x; in reset_set_enable()
852 reset = &clkrst->crc_rst_devices_y; in reset_set_enable()
931 * T210 redefines PLLP_OUT2 as PLLP_VCO/DIVP, so do different OUT1-4 setup here.
944 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
948 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]); in tegra210_setup_pllp()
953 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
959 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]); in tegra210_setup_pllp()
1015 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, in clock_early_init()
1023 clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_out[1], in clock_early_init()
1028 data = (1 << PLLD_ENABLE_CLK) | (1 << pllinfo->lock_ena); in clock_early_init()
1029 writel(data, &clkrst->crc_pll[CLOCK_ID_DISPLAY].pll_misc); in clock_early_init()
1038 value = readl(&clkrst->crc_spare_reg0); in clk_m_get_rate()
1057 writel(freq, &sysctr->cntfid0); in arch_timer_init()
1059 val = readl(&sysctr->cntcr); in arch_timer_init()
1061 writel(val, &sysctr->cntcr); in arch_timer_init()
1086 * Recovery Mode or Boot from USB", sub-section "PLLREFE". in tegra_pllref_enable()
1111 return -ETIMEDOUT; in tegra_pllref_enable()
1161 * Recovery Mode or Boot from USB", sub-section "PLLEs". in tegra_plle_enable()
1164 /* 1. Select XTAL as the source */ in tegra_plle_enable()
1213 return -ETIMEDOUT; in tegra_plle_enable()
1280 { -1, },