mach-tegra/tegra20/emc.c

1 // SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch-tegra/ap.h>
10 #include <asm/arch-tegra/apb_misc.h>
12 #include <asm/arch/emc.h>
16  * The EMC registers have shadow registers.  When the EMC clock is updated
20  * and relies on the clock lock on the emc clock to avoid races between
94 	ERR_NO_EMC_NODE = -10,
104  * Find EMC tables for the given ram code.
106  * The tegra EMC binding has two options, one using the ram code and one not.
107  * We detect which is in use by looking for the nvidia,use-ram-code property.
108  * If this is not present, then the EMC tables are directly below 'node',
109  * otherwise we select the correct emc-tables subnode based on the 'ram_code'
113  * @param node		EMC node (nvidia,tegra20-emc compatible string)
114  * @param ram_code	RAM code to select (0-3, or -1 if unknown)
115  * @return 0 if ok, otherwise a -ve ERR_ code (see enum above)
124 	need_ram_code = fdtdec_get_bool(blob, node, "nvidia,use-ram-code");  in find_emc_tables()
127 	if (ram_code == -1) {  in find_emc_tables()
144 		if (depth != 1)  in find_emc_tables()
146 		if (strcmp("emc-tables", fdt_get_name(blob, offset, NULL)))  in find_emc_tables()
149 		if (fdtdec_get_int(blob, offset, "nvidia,ram-code", -1)  in find_emc_tables()
152 	} while (1);  in find_emc_tables()
160  * Decode the EMC node of the device tree, returning a pointer to the emc
165  * @param emcp	Returns address of EMC controller registers
166  * @param tablep Returns pointer to table to program into EMC. There are
169  * @return 0 if ok, otherwise a -ve error code which will allow someone to
181 	ram_code = (readl(&pp->strapping_opt_a) & RAM_CODE_MASK)  in decode_emc()
184 	 * The EMC clock rate is twice the bus rate, and the bus rate is  in decode_emc()
191 		debug("%s: No EMC node found in FDT\n", __func__);  in decode_emc()
196 		debug("%s: No EMC node reg property\n", __func__);  in decode_emc()
200 	/* Work out the parent node which contains our EMC tables */  in decode_emc()
213 		node_rate = fdtdec_get_int(blob, node, "clock-frequency", -1);  in decode_emc()
214 		if (node_rate == -1) {  in decode_emc()
215 			debug("%s: Missing clock-frequency\n", __func__);  in decode_emc()
228 	*tablep = fdtdec_locate_array(blob, node, "nvidia,emc-registers",  in decode_emc()
242 	struct emc_ctlr *emc;  in tegra_set_emc()  local
246 	err = decode_emc(blob, rate, &emc, &table);  in tegra_set_emc()
248 		debug("Warning: no valid EMC (%d), memory timings unset\n",  in tegra_set_emc()
253 	debug("%s: Table found, setting EMC values as follows:\n", __func__);  in tegra_set_emc()
256 		u32 addr = (uintptr_t)emc + emc_reg_addr[i];  in tegra_set_emc()
262 	/* trigger emc with new settings */  in tegra_set_emc()
265 	debug("EMC clock set to %lu\n",  in tegra_set_emc()