1 // SPDX-License-Identifier: GPL-2.0+
4  * (C) Copyright 2010-2015
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/timer.h>
21  * Clock types that we can use as a source. The Tegra20 has muxes for the
23  * source. This gives us a clock 'type' and exploits what commonality exists
40 	CLOCK_TYPE_PCMT16,	/* CLOCK_TYPE_PCMT with 16-bit divider */
45 	CLOCK_TYPE_NONE = -1,	/* invalid clock type */
49 	CLOCK_MAX_MUX	= 4	/* number of source options for each clock */
53  * Clock source mux for each clock type. This just converts our enum into
56  * bits in its register for the source, we just handle it with a special
59 #define CLK(x) CLOCK_ID_ ## x  macro
61 	{ CLK(AUDIO),	CLK(XCPU),	CLK(PERIPH),	CLK(OSC)	},
62 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(AUDIO)	},
63 	{ CLK(MEMORY),	CLK(CGENERAL),	CLK(PERIPH),	CLK(OSC)	},
64 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(NONE)	},
65 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
66 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(MEMORY),	CLK(OSC)	},
67 	{ CLK(PERIPH),	CLK(CGENERAL),	CLK(XCPU),	CLK(OSC)	},
68 	{ CLK(PERIPH),	CLK(DISPLAY),	CLK(CGENERAL),	CLK(OSC)	},
73  * not in the header file since it is for purely internal use - we want
81  * use it for reset, clock enable, clock source/divider and even pinmuxing
155 	PERIPHC_NONE = -1,
159  * Clock type for each peripheral clock source. We put the name in each
238  *	SPDIF - which is both 0x08 and 0x0c
241 #define NONE(name) (-1)
398 	reg = readl(&clkrst->crc_osc_ctrl);  in clock_get_osc_freq()
402 /* Returns a pointer to the clock source register for a peripheral */
411 	assert(internal_id != -1);  in get_periph_source_reg()
412 	return &clkrst->crc_clk_src[internal_id];  in get_periph_source_reg()
421 		return -1;  in get_periph_clock_info()
425 		return -1;  in get_periph_clock_info()
429 		return -1;  in get_periph_clock_info()
432 	 * Special cases here for the clock with a 4-bit source mux and I2C  in get_periph_clock_info()
433 	 * with its 16-bit divisor  in get_periph_clock_info()
447 enum clock_id get_periph_clock_id(enum periph_id periph_id, int source)  in get_periph_clock_id()  argument
463 	return clock_source[type][source];  in get_periph_clock_id()
467  * Given a peripheral ID and the required source clock, this returns which
468  * value should be programmed into the source mux for that peripheral.
470  * There is special code here to handle the one source type with 5 sources.
473  * @param source	PLL id of required parent clock
476  * @return mux value (0-4, or -1 if not found)
494 	 * source which this peripheral can't access through its mux.  in get_periph_clock_source()
504 	return -1;  in get_periph_clock_source()
511 	u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];  in clock_set_enable()  local
516 	reg = readl(clk);  in clock_set_enable()
521 	writel(reg, clk);  in clock_set_enable()
528 	u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];  in reset_set_enable()
584 	 * TODO: Can we calculate these values instead of hard-coding?  in clock_early_init()
666 	} while (--timeout);  in tegra_plle_train()
670 		return -ETIMEDOUT;  in tegra_plle_train()
725 	} while (--timeout);  in tegra_plle_enable()
729 		return -ETIMEDOUT;  in tegra_plle_enable()
770 	{ -1, },