Lines Matching +full:detect +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015 Allwinner Technology Co.
17 /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */
37 writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN | in mctl_set_cr()
39 (para->seq ? MCTL_CR_SEQUENCE : 0) | in mctl_set_cr()
40 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) | in mctl_set_cr()
41 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
43 &mctl_com->cr); in mctl_set_cr()
48 u8 orig_rank = para->rank; in auto_detect_dram_size()
51 /* Row detect */ in auto_detect_dram_size()
52 para->page_size = 512; in auto_detect_dram_size()
53 para->seq = 1; in auto_detect_dram_size()
54 para->rows = 16; in auto_detect_dram_size()
55 para->rank = 1; in auto_detect_dram_size()
58 if (mctl_mem_matches(1 << (rows + 9))) /* row-column */ in auto_detect_dram_size()
62 /* Column (page size) detect */ in auto_detect_dram_size()
63 para->rows = 11; in auto_detect_dram_size()
64 para->page_size = 8192; in auto_detect_dram_size()
71 para->seq = 0; in auto_detect_dram_size()
72 para->rank = orig_rank; in auto_detect_dram_size()
73 para->rows = rows; in auto_detect_dram_size()
74 para->page_size = 1 << columns; in auto_detect_dram_size()
121 u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */ in auto_set_timing_para()
123 u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */ in auto_set_timing_para()
124 u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */ in auto_set_timing_para()
128 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in auto_set_timing_para()
133 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
134 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
135 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
136 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
139 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
141 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
143 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
145 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
147 writel(reg_val, &mctl_ctl->dramtmg4); in auto_set_timing_para()
149 writel(reg_val, &mctl_ctl->dramtmg5); in auto_set_timing_para()
150 /* Set two rank timing and exit self-refresh timing */ in auto_set_timing_para()
151 reg_val = readl(&mctl_ctl->dramtmg8); in auto_set_timing_para()
156 writel(reg_val, &mctl_ctl->dramtmg8); in auto_set_timing_para()
161 writel(reg_val, &mctl_ctl->pitmg0); in auto_set_timing_para()
162 /* Set phy time PTR0-2 use default */ in auto_set_timing_para()
163 writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3); in auto_set_timing_para()
164 writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4); in auto_set_timing_para()
167 writel(reg_val, &mctl_ctl->rfshtmg); in auto_set_timing_para()
175 writel(val, &mctl_ctl->pir); in mctl_set_pir()
176 mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1); in mctl_set_pir()
184 if (para->rank == 2) in mctl_data_train_cfg()
185 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24); in mctl_data_train_cfg()
187 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24); in mctl_data_train_cfg()
198 return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0; in mctl_train_dram()
207 u32 low_data_lines_status; /* Training status of datalines 0 - 7 */ in mctl_channel_init()
208 u32 high_data_lines_status; /* Training status of datalines 8 - 15 */ in mctl_channel_init()
213 clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0); in mctl_channel_init()
226 setbits_le32(&mctl_ctl->pllgcr, 0x1 << 18); in mctl_channel_init()
228 setbits_le32(&mctl_ctl->pllgcr, 0x3 << 18); in mctl_channel_init()
230 /* Auto detect dram config, set 2 rank and 16bit bus-width */ in mctl_channel_init()
231 para->cs1 = 0; in mctl_channel_init()
232 para->rank = 2; in mctl_channel_init()
233 para->bus_width = 16; in mctl_channel_init()
237 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); in mctl_channel_init()
238 clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); in mctl_channel_init()
243 writel(CONFIG_DRAM_ZQ & 0xff, &mctl_ctl->zqcr1); in mctl_channel_init()
247 writel(readl(&mctl_ctl->zqsr0) | 0x10000000, &mctl_ctl->zqcr2); in mctl_channel_init()
248 writel((CONFIG_DRAM_ZQ >> 8) & 0xff, &mctl_ctl->zqcr1); in mctl_channel_init()
256 return -EIO; in mctl_channel_init()
259 para->rank = 1; in mctl_channel_init()
266 /* Retry 16 bit bus-width with CS1 set */ in mctl_channel_init()
267 para->cs1 = 1; in mctl_channel_init()
273 /* Try 8 bit bus-width */ in mctl_channel_init()
275 para->cs1 = 0; in mctl_channel_init()
276 para->bus_width = 8; in mctl_channel_init()
279 return -EIO; in mctl_channel_init()
283 mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1); in mctl_channel_init()
286 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); in mctl_channel_init()
289 writel(0xffffffff, &mctl_com->maer); in mctl_channel_init()
303 clrsetbits_le32(&ccm->dram_pll_cfg, CCM_DRAMPLL_CFG_SRC_MASK, in mctl_sys_init()
309 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK, in mctl_sys_init()
312 mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0); in mctl_sys_init()
314 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
315 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
316 setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
317 setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
320 writel(0x0, &mctl_com->mapr); in mctl_sys_init()
321 writel(0x0f802f01, &mctl_ctl->sched); in mctl_sys_init()
322 writel(0x0000400f, &mctl_ctl->clken); /* normal */ in mctl_sys_init()
351 writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr); in sunxi_dram_init()
355 writel(0x00000303, &mctl_ctl->odtmap); in sunxi_dram_init()
357 writel(0x00000201, &mctl_ctl->odtmap); in sunxi_dram_init()