92 		&clock_manager_base->main_pll.en);  in cm_basic_init()
106 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
124 	       &clock_manager_base->main_pll.l4src);  in cm_basic_init()
127 	readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
136 	writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco);  in cm_basic_init()
147 	writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);  in cm_basic_init()
153 	writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);  in cm_basic_init()
156 	writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);  in cm_basic_init()
160 	       &clock_manager_base->main_pll.cfgs2fuser0clk);  in cm_basic_init()
169 	writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);  in cm_basic_init()
175 	       &clock_manager_base->main_pll.mainnandsdmmcclk);  in cm_basic_init()
193 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
204 	writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);  in cm_basic_init()
206 	writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);  in cm_basic_init()
208 	writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);  in cm_basic_init()
234 	u32 mainvco = readl(&clock_manager_base->main_pll.vco);  in cm_basic_init()
238 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
253 	       &clock_manager_base->main_pll.vco);  in cm_basic_init()
303 	writel(cfg->l4src, &clock_manager_base->main_pll.l4src);  in cm_basic_init()
306 	writel(~0, &clock_manager_base->main_pll.en);  in cm_basic_init()
323 	reg = readl(&clock_manager_base->main_pll.vco);  in cm_get_main_vco_clk_hz()
367 	reg = readl(&clock_manager_base->main_pll.mpuclk);  in cm_get_mpu_clk_hz()
408 	reg = readl(&clock_manager_base->main_pll.l4src);  in cm_get_l4_sp_clk_hz()
418 		reg = readl(&clock_manager_base->main_pll.mainclk);  in cm_get_l4_sp_clk_hz()
429 	reg = readl(&clock_manager_base->main_pll.maindiv);  in cm_get_l4_sp_clk_hz()
452 		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);  in cm_get_mmc_controller_clk_hz()
482 		reg = readl(&clock_manager_base->main_pll.mainqspiclk);  in cm_get_qspi_controller_clk_hz()