151 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */  in dpll3_init_34xx()
153 				0xF8000000, ptr->m2 << 27);  in dpll3_init_34xx()
206 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */  in dpll3_init_34xx()
207 		clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);  in dpll3_init_34xx()
264 	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */  in dpll4_init_34xx()
265 	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1));  in dpll4_init_34xx()
266 	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);  in dpll4_init_34xx()
295 	/* set M2 (usbtll_fck) */  in dpll5_init_34xx()
296 	clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);  in dpll5_init_34xx()
318 	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */  in mpu_init_34xx()
320 			0x0000001F, ptr->m2);  in mpu_init_34xx()
349 	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */  in iva_init_34xx()
351 			0x0000001F, ptr->m2);  in iva_init_34xx()
401 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */  in dpll3_init_36xx()
403 				0xF8000000, ptr->m2 << 27);  in dpll3_init_36xx()
456 		/* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */  in dpll3_init_36xx()
457 		clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27);  in dpll3_init_36xx()
507 	/* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */  in dpll4_init_36xx()
508 	clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2);  in dpll4_init_36xx()
535 	/* set M2 (usbtll_fck) */  in dpll5_init_36xx()
536 	clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2);  in dpll5_init_36xx()
556 	/* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */  in mpu_init_36xx()
557 	clrsetbits_le32(&prcm_base->clksel2_pll_mpu, 0x0000001F, ptr->m2);  in mpu_init_36xx()
579 	/* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */  in iva_init_36xx()
580 	clrsetbits_le32(&prcm_base->clksel2_pll_iva2, 0x0000001F, ptr->m2);  in iva_init_36xx()