1 // SPDX-License-Identifier: GPL-2.0+
6  * (C) Copyright 2004-2008
14  *      Richard Woodruff <r-woodruff2@ti.com>
77 	struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;  in secure_unlock_mem()
78 	struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;  in secure_unlock_mem()
79 	struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;  in secure_unlock_mem()
80 	struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;  in secure_unlock_mem()
84 	writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);  in secure_unlock_mem()
85 	writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);  in secure_unlock_mem()
86 	writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);  in secure_unlock_mem()
87 	writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);  in secure_unlock_mem()
89 	writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);  in secure_unlock_mem()
90 	writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);  in secure_unlock_mem()
91 	writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);  in secure_unlock_mem()
93 	writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);  in secure_unlock_mem()
94 	writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);  in secure_unlock_mem()
95 	writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);  in secure_unlock_mem()
96 	writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);  in secure_unlock_mem()
99 	writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);  in secure_unlock_mem()
100 	writel(UNLOCK_3, &pm_iva2_base->read_permission_0);  in secure_unlock_mem()
101 	writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);  in secure_unlock_mem()
104 	writel(UNLOCK_1, &sms_base->rg_att0);  in secure_unlock_mem()
111  *              general use.
117 	/* configure non-secure access control register */  in secureworld_exit()
119 	/* enabling co-processor CP10 and CP11 accesses in NS world */  in secureworld_exit()
123 	 * allow use of PLE registers in NS world also  in secureworld_exit()
142  *              general use.
150 	 * if GP device unlock device SRAM for general use  in try_unlock_memory()
151 	 * secure code breaks for Secure/Emulation device - HS/E/T  in try_unlock_memory()
181  *              - Called path is with SRAM stack.
191 	/* Invalidate L2-cache from secure mode */  in s_init()
240 		pending = readl(&wd_base->wwps);  in wait_for_command_complete()
256 	 * We need to take care of WD2-MPU or take a PRCM reset. WD3  in watchdog_init()
260 	setbits_le32(&prcm_base->fclken_wkup, 0x20);  in watchdog_init()
261 	setbits_le32(&prcm_base->iclken_wkup, 0x20);  in watchdog_init()
262 	wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);  in watchdog_init()
264 	writel(WD_UNLOCK1, &wd2_base->wspr);  in watchdog_init()
266 	writel(WD_UNLOCK2, &wd2_base->wspr);  in watchdog_init()
278  * OMAP3 specific command to switch between NAND HW and SW ecc
297 	} else if (strncmp(argv[1], "sw", 2) == 0) {  in do_switch_ecc()
309 	return -omap_nand_switch_ecc(hw, strength);  in do_switch_ecc()
312 	printf ("Usage: nandecc %s\n", cmdtp->usage);  in do_switch_ecc()
319 	"hw [hamming|bch8|bch16] - Switch between NAND hardware 1-bit hamming"
320 	" and 8-bit/16-bit BCH\n"
323 	"nandecc sw               - Switch to NAND software ecc algorithm."
354 	 * copy the parameters to an un-cached area to avoid coherency  in omap3_emu_romcode_call()
390 	/* Write ACR - affects secure banked bits */  in v7_arch_cp15_set_acr()
396 	/* Write ACR - affects non-secure banked bits - some erratas need it */  in v7_arch_cp15_set_acr()