Lines Matching +full:1 +full:khz
151 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
153 pcc_clock_div_config(PER_CLK_USDHC0, false, 1); in init_clk_usdhc()
156 case 1: in init_clk_usdhc()
160 /* 158MHz / 1 = 158MHz */ in init_clk_usdhc()
162 pcc_clock_div_config(PER_CLK_USDHC1, false, 1); in init_clk_usdhc()
204 if (CONFIG_USB_MAX_CONTROLLER_COUNT > 1) { in enable_usboh3_clk()
290 * 1. Enable PFD1-3 of APLL for A7 side. Enable FIRC and DIVs. in clock_init()
312 enable_usboh3_clk(1); in clock_init()
344 printf("CORE %8d kHz\n", scg_clk_get_rate(SCG_CORE_CLK) / 1000); in do_mx7_showclocks()
345 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); in do_mx7_showclocks()
346 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); in do_mx7_showclocks()
347 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); in do_mx7_showclocks()
348 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); in do_mx7_showclocks()
349 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); in do_mx7_showclocks()
350 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); in do_mx7_showclocks()
351 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); in do_mx7_showclocks()
352 printf("I2C4 %8d kHz\n", mxc_get_clock(MXC_I2C_CLK) / 1000); in do_mx7_showclocks()
362 clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,