Lines Matching +full:anatop +full:- +full:reg +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
16 #include <asm/mach-imx/boot_mode.h>
17 #include <asm/mach-imx/dma.h>
18 #include <asm/mach-imx/hab.h>
63 return readl(&scu->config) & 3; in get_nr_cpus()
68 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in get_cpu_rev() local
69 u32 reg = readl(&anatop->digprog_sololite); in get_cpu_rev() local
70 u32 type = ((reg >> 16) & 0xff); in get_cpu_rev()
74 reg = readl(&anatop->digprog); in get_cpu_rev()
76 cfg = readl(&scu->config) & 3; in get_cpu_rev()
77 type = ((reg >> 16) & 0xff); in get_cpu_rev()
89 major = ((reg >> 8) & 0xff); in get_cpu_rev()
92 major--; in get_cpu_rev()
97 reg &= 0xff; /* mx6 silicon revision */ in get_cpu_rev()
98 return (type << 12) | (reg + (0x10 * (major + 1))); in get_cpu_rev()
102 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
103 * defines a 2-bit SPEED_GRADING
126 struct fuse_bank *bank = &ocotp->bank[0]; in get_cpu_speed_grade_hz()
128 (struct fuse_bank0_regs *)bank->fuse_regs; in get_cpu_speed_grade_hz()
131 val = readl(&fuse->cfg3); in get_cpu_speed_grade_hz()
175 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
176 * defines a 2-bit Temperature Grade
185 struct fuse_bank *bank = &ocotp->bank[1]; in get_cpu_temp_grade()
187 (struct fuse_bank1_regs *)bank->fuse_regs; in get_cpu_temp_grade()
190 val = readl(&fuse->mem0); in get_cpu_temp_grade()
196 *minc = -40; in get_cpu_temp_grade()
199 *minc = -40; in get_cpu_temp_grade()
202 *minc = -20; in get_cpu_temp_grade()
229 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in clear_ldo_ramp() local
230 int reg; in clear_ldo_ramp() local
236 reg = readl(&anatop->ana_misc2); in clear_ldo_ramp()
237 reg &= ~(0x3f << 24); in clear_ldo_ramp()
238 writel(reg, &anatop->ana_misc2); in clear_ldo_ramp()
250 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in set_ldo_voltage() local
251 u32 val, step, old, reg = readl(&anatop->reg_core); in set_ldo_voltage() local
263 val = (mv - 700) / 25; in set_ldo_voltage()
278 return -EINVAL; in set_ldo_voltage()
281 old = (reg & (0x1F << shift)) >> shift; in set_ldo_voltage()
282 step = abs(val - old); in set_ldo_voltage()
286 reg = (reg & ~(0x1F << shift)) | (val << shift); in set_ldo_voltage()
287 writel(reg, &anatop->reg_core); in set_ldo_voltage()
290 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per in set_ldo_voltage()
301 u32 reg, div; in set_ahb_rate() local
303 div = get_periph_clk() / val - 1; in set_ahb_rate()
304 reg = readl(&mxc_ccm->cbcdr); in set_ahb_rate()
306 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) | in set_ahb_rate()
307 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr); in set_ahb_rate()
313 u32 reg; in clear_mmdc_ch_mask() local
314 reg = readl(&mxc_ccm->ccdr); in clear_mmdc_ch_mask()
318 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); in clear_mmdc_ch_mask()
320 reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); in clear_mmdc_ch_mask()
321 writel(reg, &mxc_ccm->ccdr); in clear_mmdc_ch_mask()
328 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in init_bandgap() local
330 struct fuse_bank *bank = &ocotp->bank[1]; in init_bandgap()
332 (struct fuse_bank1_regs *)bank->fuse_regs; in init_bandgap()
338 while (!(readl(&anatop->ana_misc0) & 0x80)) in init_bandgap()
345 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); in init_bandgap()
349 * 000 - set REFTOP_VBGADJ[2:0] to 3b'110, in init_bandgap()
350 * 110 - set REFTOP_VBGADJ[2:0] to 3b'000, in init_bandgap()
351 * 001 - set REFTOP_VBGADJ[2:0] to 3b'001, in init_bandgap()
352 * 010 - set REFTOP_VBGADJ[2:0] to 3b'010, in init_bandgap()
353 * 011 - set REFTOP_VBGADJ[2:0] to 3b'011, in init_bandgap()
354 * 100 - set REFTOP_VBGADJ[2:0] to 3b'100, in init_bandgap()
355 * 101 - set REFTOP_VBGADJ[2:0] to 3b'101, in init_bandgap()
356 * 111 - set REFTOP_VBGADJ[2:0] to 3b'111, in init_bandgap()
359 val = readl(&fuse->mem0); in init_bandgap()
364 &anatop->ana_misc0_set); in init_bandgap()
378 * Disable self-bias circuit in the analog bandap. in arch_cpu_init()
379 * The self-bias circuit is used by the bandgap during startup. in arch_cpu_init()
427 * register offset is different from i.MX6UL, since in arch_cpu_init()
436 setbits_le32(&ccm->cscmr1, MXC_CCM_CSCMR1_PER_CLK_SEL_MASK); in arch_cpu_init()
441 setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); in arch_cpu_init()
457 u32 soc_sbmr = readl(&src_regs->sbmr1); in mmc_get_boot_dev()
471 return -1; in mmc_get_boot_dev()
560 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; in s_init() local
564 u32 reg, periph1, periph2; in s_init() local
582 reg = readl(&ccm->cbcmr); in s_init()
583 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) in s_init()
585 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) in s_init()
596 writel(mask480, &anatop->pfd_480_set); in s_init()
597 writel(mask528, &anatop->pfd_528_set); in s_init()
598 writel(mask480, &anatop->pfd_480_clr); in s_init()
599 writel(mask528, &anatop->pfd_528_clr); in s_init()
606 u8 reg; in imx_enable_hdmi_phy() local
607 reg = readb(&hdmi->phy_conf0); in imx_enable_hdmi_phy()
608 reg |= HDMI_PHY_CONF0_PDZ_MASK; in imx_enable_hdmi_phy()
609 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
611 reg |= HDMI_PHY_CONF0_ENTMDS_MASK; in imx_enable_hdmi_phy()
612 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
614 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK; in imx_enable_hdmi_phy()
615 writeb(reg, &hdmi->phy_conf0); in imx_enable_hdmi_phy()
616 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz); in imx_enable_hdmi_phy()
623 int reg, count; in imx_setup_hdmi() local
627 reg = readl(&mxc_ccm->CCGR2); in imx_setup_hdmi()
628 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK| in imx_setup_hdmi()
630 writel(reg, &mxc_ccm->CCGR2); in imx_setup_hdmi()
631 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz); in imx_setup_hdmi()
632 reg = readl(&mxc_ccm->chsccdr); in imx_setup_hdmi()
633 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK| in imx_setup_hdmi()
636 reg |= (CHSCCDR_PODF_DIVIDE_BY_3 in imx_setup_hdmi()
640 writel(reg, &mxc_ccm->chsccdr); in imx_setup_hdmi()
643 if (readb(&hdmi->ih_fc_stat2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) { in imx_setup_hdmi()
645 writeb((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, &hdmi->mc_swrstz); in imx_setup_hdmi()
646 val = readb(&hdmi->fc_invidconf); in imx_setup_hdmi()
649 writeb(val, &hdmi->fc_invidconf); in imx_setup_hdmi()
672 writel(0xF00000CF, &iomux->gpr[4]); in gpr_init()
674 /* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ in gpr_init()
675 writel(0x77177717, &iomux->gpr[6]); in gpr_init()
676 writel(0x77177717, &iomux->gpr[7]); in gpr_init()
678 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ in gpr_init()
679 writel(0x007F007F, &iomux->gpr[6]); in gpr_init()
680 writel(0x007F007F, &iomux->gpr[7]); in gpr_init()