Lines Matching refs:CCGR3
104 addr = &imx_ccm->CCGR3; in enable_enet_clk()
803 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
806 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
814 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
817 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
826 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
828 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
841 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
843 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
863 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
874 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
953 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
955 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
973 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
975 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
1319 reg = readl(&mxc_ccm->CCGR3); in enable_ipu_clock()
1321 writel(reg, &mxc_ccm->CCGR3); in enable_ipu_clock()
1325 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); in enable_ipu_clock()