Lines Matching +full:anatop +full:- +full:enable +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
10 #include <asm/arch/imx-regs.h>
27 void enable_ocotp_clk(unsigned char enable) in enable_ocotp_clk() argument
31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
32 if (enable) in enable_ocotp_clk()
36 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
44 clrbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
52 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
54 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
60 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
62 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_io_clk()
64 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
70 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_io_clk()
72 setbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
81 void enable_usboh3_clk(unsigned char enable) in enable_usboh3_clk() argument
85 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
86 if (enable) in enable_usboh3_clk()
90 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
95 void enable_enet_clk(unsigned char enable) in enable_enet_clk() argument
101 addr = &imx_ccm->CCGR0; in enable_enet_clk()
104 addr = &imx_ccm->CCGR3; in enable_enet_clk()
107 addr = &imx_ccm->CCGR1; in enable_enet_clk()
110 if (enable) in enable_enet_clk()
118 void enable_uart_clk(unsigned char enable) in enable_uart_clk() argument
127 if (enable) in enable_uart_clk()
128 setbits_le32(&imx_ccm->CCGR5, mask); in enable_uart_clk()
130 clrbits_le32(&imx_ccm->CCGR5, mask); in enable_uart_clk()
135 int enable_usdhc_clk(unsigned char enable, unsigned bus_num) in enable_usdhc_clk() argument
140 return -EINVAL; in enable_usdhc_clk()
143 if (enable) in enable_usdhc_clk()
144 setbits_le32(&imx_ccm->CCGR6, mask); in enable_usdhc_clk()
146 clrbits_le32(&imx_ccm->CCGR6, mask); in enable_usdhc_clk()
153 /* i2c_num can be from 0 - 3 */
154 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) in enable_i2c_clk() argument
161 return -EINVAL; in enable_i2c_clk()
166 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
167 if (enable) in enable_i2c_clk()
171 __raw_writel(reg, &imx_ccm->CCGR2); in enable_i2c_clk()
174 return -EINVAL; in enable_i2c_clk()
177 addr = &imx_ccm->CCGR6; in enable_i2c_clk()
180 addr = &imx_ccm->CCGR1; in enable_i2c_clk()
183 if (enable) in enable_i2c_clk()
193 /* spi_num can be from 0 - SPI_MAX_NUM */
194 int enable_spi_clk(unsigned char enable, unsigned spi_num) in enable_spi_clk() argument
200 return -EINVAL; in enable_spi_clk()
203 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
204 if (enable) in enable_spi_clk()
208 __raw_writel(reg, &imx_ccm->CCGR1); in enable_spi_clk()
217 div = __raw_readl(&imx_ccm->analog_pll_sys); in decode_pll()
222 div = __raw_readl(&imx_ccm->analog_pll_528); in decode_pll()
227 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); in decode_pll()
232 div = __raw_readl(&imx_ccm->analog_pll_enet); in decode_pll()
237 div = __raw_readl(&imx_ccm->analog_pll_audio); in decode_pll()
243 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num); in decode_pll()
244 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom); in decode_pll()
252 test_div = 1 << (2 - test_div); in decode_pll()
256 div = __raw_readl(&imx_ccm->analog_pll_video); in decode_pll()
262 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num); in decode_pll()
263 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom); in decode_pll()
271 test_div = 1 << (2 - test_div); in decode_pll()
292 div = __raw_readl(&imx_ccm->analog_pfd_528); in mxc_get_pll_pfd()
296 div = __raw_readl(&imx_ccm->analog_pfd_480); in mxc_get_pll_pfd()
312 reg = __raw_readl(&imx_ccm->cacrr); in get_mcu_main_clk()
324 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
328 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
344 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
374 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
385 reg = __raw_readl(&imx_ccm->cscmr1); in get_ipg_per_clk()
401 reg = __raw_readl(&imx_ccm->cscdr1); in get_uart_clk()
419 reg = __raw_readl(&imx_ccm->cscdr2); in get_cspi_clk()
435 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk()
455 cscmr1 = __raw_readl(&imx_ccm->cscmr1); in get_emi_slow_clk()
481 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); in get_mmdc_ch0_clk()
482 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk()
524 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2)); in get_mmdc_ch0_clk()
565 &imx_ccm->analog_pll_video_clr); in enable_pll_video()
572 &imx_ccm->analog_pll_video_set); in enable_pll_video()
577 &imx_ccm->analog_pll_video_set); in enable_pll_video()
582 &imx_ccm->analog_pll_video_set); in enable_pll_video()
586 return -EINVAL; in enable_pll_video()
590 &imx_ccm->analog_pll_video_num); in enable_pll_video()
592 &imx_ccm->analog_pll_video_denom); in enable_pll_video()
598 reg = readl(&imx_ccm->analog_pll_video); in enable_pll_video()
600 /* Enable PLL out */ in enable_pll_video()
602 &imx_ccm->analog_pll_video_set); in enable_pll_video()
609 return -ETIME; in enable_pll_video()
613 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
638 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
639 /* Can't change clocks when clock not from pre-mux */ in mxs_set_lcdclk()
646 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
647 /* Can't change clocks when clock not from pre-mux */ in mxs_set_lcdclk()
656 * Bit Field: POST_DIV_SELECT in mxs_set_lcdclk()
699 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
703 * (24MHz * (pll_div + --------- )) in mxs_set_lcdclk()
705 *freq KHz = -------------------------------- in mxs_set_lcdclk()
715 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
716 clrsetbits_le32(&imx_ccm->cscdr2, in mxs_set_lcdclk()
720 ((pred - 1) << in mxs_set_lcdclk()
724 clrsetbits_le32(&imx_ccm->cbcmr, in mxs_set_lcdclk()
726 ((postd - 1) << in mxs_set_lcdclk()
729 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
730 clrsetbits_le32(&imx_ccm->cscdr2, in mxs_set_lcdclk()
734 ((pred - 1) << in mxs_set_lcdclk()
738 clrsetbits_le32(&imx_ccm->cscmr1, in mxs_set_lcdclk()
740 (((postd - 1)^0x6) << in mxs_set_lcdclk()
751 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
752 clrsetbits_le32(&imx_ccm->cscdr2, in mxs_set_lcdclk()
756 ((pred - 1) << in mxs_set_lcdclk()
760 clrsetbits_le32(&imx_ccm->cscmr1, in mxs_set_lcdclk()
762 ((postd - 1) << in mxs_set_lcdclk()
769 int enable_lcdif_clock(u32 base_addr, bool enable) in enable_lcdif_clock() argument
778 return -EINVAL; in enable_lcdif_clock()
780 /* Set to pre-mux clock at default */ in enable_lcdif_clock()
792 return -EINVAL; in enable_lcdif_clock()
794 /* Set to pre-mux clock at default */ in enable_lcdif_clock()
800 return -EINVAL; in enable_lcdif_clock()
803 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
806 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
808 if (enable) { in enable_lcdif_clock()
809 reg = readl(&imx_ccm->cscdr3); in enable_lcdif_clock()
812 writel(reg, &imx_ccm->cscdr3); in enable_lcdif_clock()
814 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
817 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
826 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
828 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
830 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
832 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
834 if (enable) { in enable_lcdif_clock()
835 /* Select pre-mux */ in enable_lcdif_clock()
836 reg = readl(&imx_ccm->cscdr2); in enable_lcdif_clock()
838 writel(reg, &imx_ccm->cscdr2); in enable_lcdif_clock()
840 /* Enable the LCDIF pix clock */ in enable_lcdif_clock()
841 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
843 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
845 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
847 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
855 /* qspi_num can be from 0 - 1 */
859 /* Enable QuadSPI clock */ in enable_qspi_clk()
863 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
866 reg = readl(&imx_ccm->cscmr1); in enable_qspi_clk()
871 writel(reg, &imx_ccm->cscmr1); in enable_qspi_clk()
873 /* enable the clock gate */ in enable_qspi_clk()
874 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
882 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | in enable_qspi_clk()
886 reg = readl(&imx_ccm->cs2cdr); in enable_qspi_clk()
892 writel(reg, &imx_ccm->cs2cdr); in enable_qspi_clk()
894 /*enable the clock gate*/ in enable_qspi_clk()
895 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | in enable_qspi_clk()
910 struct anatop_regs __iomem *anatop = in enable_fec_anatop_clock() local
914 return -EINVAL; in enable_fec_anatop_clock()
916 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()
924 return -EINVAL; in enable_fec_anatop_clock()
928 return -EINVAL; in enable_fec_anatop_clock()
934 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
935 while (timeout--) { in enable_fec_anatop_clock()
936 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) in enable_fec_anatop_clock()
940 return -ETIMEDOUT; in enable_fec_anatop_clock()
943 /* Enable FEC clock */ in enable_fec_anatop_clock()
949 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
953 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
955 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
959 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB in enable_fec_anatop_clock()
961 reg = readl(&imx_ccm->chsccdr); in enable_fec_anatop_clock()
970 writel(reg, &imx_ccm->chsccdr); in enable_fec_anatop_clock()
972 /* Enable enet system clock */ in enable_fec_anatop_clock()
973 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
975 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
984 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); in get_usdhc_clk()
985 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); in get_usdhc_clk()
1052 /* Enable PLLs */ in enable_enet_pll()
1053 reg = readl(&imx_ccm->analog_pll_enet); in enable_enet_pll()
1055 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1057 while (timeout--) { in enable_enet_pll()
1058 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) in enable_enet_pll()
1062 return -EIO; in enable_enet_pll()
1064 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1066 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1077 /* Enable SATA clock. */ in ungate_sata_clock()
1078 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); in ungate_sata_clock()
1092 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); in disable_sata_clock()
1102 /* Enable PCIe clock. */ in ungate_pcie_clock()
1103 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); in ungate_pcie_clock()
1117 * MX6RM. The register that is mapped in the ANATOP space and in enable_pcie_clock()
1122 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important in enable_pcie_clock()
1136 clrsetbits_le32(&anatop_regs->ana_misc1, in enable_pcie_clock()
1142 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); in enable_pcie_clock()
1156 void hab_caam_clock_enable(unsigned char enable) in hab_caam_clock_enable() argument
1162 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1163 if (enable) in hab_caam_clock_enable()
1167 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1170 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1171 if (enable) in hab_caam_clock_enable()
1179 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1183 reg = __raw_readl(&imx_ccm->CCGR6); in hab_caam_clock_enable()
1184 if (enable) in hab_caam_clock_enable()
1188 __raw_writel(reg, &imx_ccm->CCGR6); in hab_caam_clock_enable()
1194 struct anatop_regs __iomem *anatop = in enable_pll3() local
1198 if ((readl(&anatop->usb1_pll_480_ctrl) & in enable_pll3()
1200 /* enable pll's power */ in enable_pll3()
1202 &anatop->usb1_pll_480_ctrl_set); in enable_pll3()
1203 writel(0x80, &anatop->ana_misc2_clr); in enable_pll3()
1205 while ((readl(&anatop->usb1_pll_480_ctrl) & in enable_pll3()
1210 &anatop->usb1_pll_480_ctrl_clr); in enable_pll3()
1211 /* enable pll output */ in enable_pll3()
1213 &anatop->usb1_pll_480_ctrl_set); in enable_pll3()
1223 void enable_eim_clk(unsigned char enable) in enable_eim_clk() argument
1227 reg = __raw_readl(&imx_ccm->CCGR6); in enable_eim_clk()
1228 if (enable) in enable_eim_clk()
1232 __raw_writel(reg, &imx_ccm->CCGR6); in enable_eim_clk()
1319 reg = readl(&mxc_ccm->CCGR3); in enable_ipu_clock()
1321 writel(reg, &mxc_ccm->CCGR3); in enable_ipu_clock()
1324 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); in enable_ipu_clock()
1325 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); in enable_ipu_clock()
1338 reg = readl(&mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1344 writel(reg, &mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1347 reg = readl(&mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1349 writel(reg, &mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1352 reg = readl(&mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1354 writel(reg, &mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1362 reg = readl(&mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1367 writel(reg, &mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1369 reg = readl(&mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1371 writel(reg, &mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1389 * no CG bit. in select_ldb_di_clock_source()
1398 * Need to disable MMDC_CH1 clock manually as there is no CG bit in select_ldb_di_clock_source()
1407 /* Set MMDC_CH1 mask bit */ in select_ldb_di_clock_source()
1408 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1410 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()
1413 reg = readl(&mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1415 writel(reg, &mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1421 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1423 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1426 while (readl(&mxc_ccm->cdhipr)) in select_ldb_di_clock_source()
1429 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1431 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1434 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1437 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1440 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1445 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1448 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1453 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1456 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1458 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1464 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1466 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1469 while (readl(&mxc_ccm->cdhipr)) in select_ldb_di_clock_source()
1471 /* Clear MMDC_CH1 mask bit */ in select_ldb_di_clock_source()
1472 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1474 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()