Lines Matching +full:0 +full:x3
14 unsigned char res1[0x10];
27 unsigned char res2[0x4];
68 unsigned char res3[0x288];
71 unsigned char res4[0x10];
78 unsigned char res5[0xc];
81 unsigned char res6[0x2c];
87 unsigned char res7[0x8];
90 unsigned char res8[0x1c];
92 unsigned char res9[0x200];
98 unsigned char res10[0x2c];
100 unsigned char res[0x4];
102 unsigned char res11[0x34];
113 unsigned char res12[0x1c];
119 unsigned char res13[0x14];
122 unsigned char res14[0x1c];
134 unsigned char res15[0x8];
137 unsigned char res16[0x8];
142 unsigned char res17[0x18];
145 unsigned char res18[0x10];
147 unsigned char res50[0x4];
160 unsigned char res19[0x18];
162 unsigned char res20[0x3c];
165 unsigned char res21[0x8c];
168 unsigned char res22[0x8];
189 unsigned char res24[0x30];
191 unsigned char res25[0xc];
193 unsigned char res26[0x1c];
201 #define VIDEO_EN_MASK (0x01 << 7)
202 #define VIDEO_MUTE_MASK (0x01 << 6)
205 #define VIDEO_BIST_MASK (0x1 << 3)
208 #define SEL_BG_NEW_BANDGAP (0x0 << 6)
209 #define SEL_BG_INTERNAL_RESISTOR (0x1 << 6)
210 #define TX_TERMINAL_CTRL_73_OHM (0x0 << 4)
211 #define TX_TERMINAL_CTRL_61_OHM (0x1 << 4)
212 #define TX_TERMINAL_CTRL_50_OHM (0x2 << 4)
213 #define TX_TERMINAL_CTRL_45_OHM (0x3 << 4)
214 #define SWING_A_30PER_G_INCREASE (0x1 << 3)
215 #define SWING_A_30PER_G_NORMAL (0x0 << 3)
218 #define CPREG_BLEED (0x1 << 4)
219 #define SEL_24M (0x1 << 3)
220 #define TX_DVDD_BIT_1_0000V (0x3 << 0)
221 #define TX_DVDD_BIT_1_0625V (0x4 << 0)
222 #define TX_DVDD_BIT_1_1250V (0x5 << 0)
225 #define DRIVE_DVDD_BIT_1_0000V (0x3 << 5)
226 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
227 #define DRIVE_DVDD_BIT_1_1250V (0x5 << 5)
228 #define SEL_CURRENT_DEFAULT (0x0 << 3)
229 #define VCO_BIT_000_MICRO (0x0 << 0)
230 #define VCO_BIT_200_MICRO (0x1 << 0)
231 #define VCO_BIT_300_MICRO (0x2 << 0)
232 #define VCO_BIT_400_MICRO (0x3 << 0)
233 #define VCO_BIT_500_MICRO (0x4 << 0)
234 #define VCO_BIT_600_MICRO (0x5 << 0)
235 #define VCO_BIT_700_MICRO (0x6 << 0)
236 #define VCO_BIT_900_MICRO (0x7 << 0)
239 #define PD_RING_OSC (0x1 << 6)
240 #define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4)
241 #define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4)
242 #define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4)
243 #define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4)
244 #define TX_CUR1_1X (0x0 << 2)
245 #define TX_CUR1_2X (0x1 << 2)
246 #define TX_CUR1_3X (0x2 << 2)
247 #define TX_CUR_1_MA (0x0 << 0)
248 #define TX_CUR_2_MA (0x1 << 0)
249 #define TX_CUR_3_MA (0x2 << 0)
250 #define TX_CUR_4_MA (0x3 << 0)
253 #define CH3_AMP_0_MV (0x3 << 12)
254 #define CH2_AMP_0_MV (0x3 << 8)
255 #define CH1_AMP_0_MV (0x3 << 4)
256 #define CH0_AMP_0_MV (0x3 << 0)
259 #define DP_PLL_PD (0x1 << 7)
260 #define DP_PLL_RESET (0x1 << 6)
261 #define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4)
262 #define DP_PLL_REF_BIT_1_1250V (0x5 << 0)
263 #define DP_PLL_REF_BIT_1_2500V (0x7 << 0)
266 #define SOFT_INT_CTRL (0x1 << 2)
267 #define INT_POL (0x1 << 0)
270 #define RESET_DP_TX (0x01 << 0)
273 #define MASTER_VID_FUNC_EN_N (0x1 << 7)
274 #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
275 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
276 #define AUD_FUNC_EN_N (0x1 << 3)
277 #define HDCP_FUNC_EN_N (0x1 << 2)
278 #define CRC_FUNC_EN_N (0x1 << 1)
279 #define SW_FUNC_EN_N (0x1 << 0)
282 #define SSC_FUNC_EN_N (0x1 << 7)
283 #define AUX_FUNC_EN_N (0x1 << 2)
284 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
285 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
288 #define PHY_PD (0x1 << 5)
289 #define AUX_PD (0x1 << 4)
290 #define CH3_PD (0x1 << 3)
291 #define CH2_PD (0x1 << 2)
292 #define CH1_PD (0x1 << 1)
293 #define CH0_PD (0x1 << 0)
296 #define VSYNC_DET (0x1 << 7)
297 #define PLL_LOCK_CHG (0x1 << 6)
298 #define SPDIF_ERR (0x1 << 5)
299 #define SPDIF_UNSTBL (0x1 << 4)
300 #define VID_FORMAT_CHG (0x1 << 3)
301 #define AUD_CLK_CHG (0x1 << 2)
302 #define VID_CLK_CHG (0x1 << 1)
303 #define SW_INT (0x1 << 0)
306 #define PLL_LOCK (0x1 << 4)
307 #define F_PLL_LOCK (0x1 << 3)
308 #define PLL_LOCK_CTRL (0x1 << 2)
311 #define SSC_FUNC_EN_N (0x1 << 7)
312 #define AUX_FUNC_EN_N (0x1 << 2)
313 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
314 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
317 #define PSR_ACTIVE (0x1 << 7)
318 #define PSR_INACTIVE (0x1 << 6)
319 #define SPDIF_BI_PHASE_ERR (0x1 << 5)
320 #define HOTPLUG_CHG (0x1 << 2)
321 #define HPD_LOST (0x1 << 1)
322 #define PLUG (0x1 << 0)
325 #define INT_HPD (0x1 << 6)
326 #define HW_TRAINING_FINISH (0x1 << 5)
327 #define RPLY_RECEIV (0x1 << 1)
328 #define AUX_ERR (0x1 << 0)
331 #define HPD_STATUS (0x1 << 6)
332 #define F_HPD (0x1 << 5)
333 #define HPD_CTRL (0x1 << 4)
334 #define HDCP_RDY (0x1 << 3)
335 #define STRM_VALID (0x1 << 2)
336 #define F_VALID (0x1 << 1)
337 #define VALID_CTRL (0x1 << 0)
340 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8)
341 #define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3)
342 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3)
343 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3)
344 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
345 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
346 #define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0)
349 #define DEFER_CTRL_EN (0x1 << 7)
350 #define DEFER_COUNT(x) (((x) & 0x7f) << 0)
352 #define COMMON_INT_MASK_1 (0)
353 #define COMMON_INT_MASK_2 (0)
354 #define COMMON_INT_MASK_3 (0)
355 #define COMMON_INT_MASK_4 (0)
356 #define INT_STA_MASK (0)
359 #define BUF_CLR (0x1 << 7)
360 #define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0)
363 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
366 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
369 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
372 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
373 #define AUX_TX_COMM_MASK (0xf << 0)
374 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
375 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
376 #define AUX_TX_COMM_MOT (0x1 << 2)
377 #define AUX_TX_COMM_WRITE (0x0 << 0)
378 #define AUX_TX_COMM_READ (0x1 << 0)
381 #define ADDR_ONLY (0x1 << 1)
382 #define AUX_EN (0x1 << 0)
385 #define AUX_BUSY (0x1 << 4)
386 #define AUX_STATUS_MASK (0xf << 0)
389 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
390 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
393 #define MACRO_RST (0x1 << 5)
394 #define CH1_TEST (0x1 << 1)
395 #define CH0_TEST (0x1 << 0)
398 #define SCRAMBLER_TYPE (0x1 << 9)
399 #define HW_LINK_TRAINING_PATTERN (0x1 << 8)
400 #define SCRAMBLING_DISABLE (0x1 << 5)
401 #define SCRAMBLING_ENABLE (0x0 << 5)
402 #define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2)
403 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
404 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
405 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
406 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
407 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
408 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
409 #define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0)
412 #define TOTAL_LINE_CFG_L(x) ((x) & 0xff)
413 #define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff)
414 #define ACTIVE_LINE_CFG_L(x) ((x) & 0xff)
415 #define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff)
416 #define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff)
417 #define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
418 #define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff)
419 #define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff)
421 #define H_F_PORCH_CFG_L(x) ((x) & 0xff)
422 #define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
423 #define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff)
424 #define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
425 #define H_B_PORCH_CFG_L(x) ((x) & 0xff)
426 #define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff)
429 #define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5)
430 #define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3)
431 #define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3)
432 #define PRE_EMPHASIS_SET_0_MASK (0x3 << 3)
434 #define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3)
435 #define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3)
436 #define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3)
437 #define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3)
438 #define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2)
439 #define DRIVE_CURRENT_SET_0_MASK (0x3 << 0)
440 #define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0)
441 #define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3)
442 #define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0)
443 #define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0)
444 #define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0)
445 #define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0)
448 #define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5)
449 #define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3)
450 #define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3)
451 #define PRE_EMPHASIS_SET_1_MASK (0x3 << 3)
453 #define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3)
454 #define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3)
455 #define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3)
456 #define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3)
457 #define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2)
458 #define DRIVE_CURRENT_SET_1_MASK (0x3 << 0)
459 #define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0)
460 #define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3)
461 #define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0)
462 #define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0)
463 #define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0)
464 #define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0)
467 #define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5)
468 #define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3)
469 #define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3)
470 #define PRE_EMPHASIS_SET_2_MASK (0x3 << 3)
472 #define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3)
473 #define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3)
474 #define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3)
475 #define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3)
476 #define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2)
477 #define DRIVE_CURRENT_SET_2_MASK (0x3 << 0)
478 #define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0)
479 #define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3)
480 #define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0)
481 #define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0)
482 #define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0)
483 #define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0)
486 #define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5)
487 #define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3)
488 #define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3)
489 #define PRE_EMPHASIS_SET_3_MASK (0x3 << 3)
491 #define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3)
492 #define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3)
493 #define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3)
494 #define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3)
495 #define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2)
496 #define DRIVE_CURRENT_SET_3_MASK (0x3 << 0)
497 #define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0)
498 #define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3)
499 #define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0)
500 #define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0)
501 #define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0)
502 #define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0)
505 #define FORMAT_SEL (0x1 << 4)
506 #define INTERACE_SCAN_CFG (0x1 << 2)
508 #define VSYNC_POLARITY_CFG (0x1 << 1)
510 #define HSYNC_POLARITY_CFG (0x1 << 0)
511 #define H_S_POLARITY_CFG_SHIFT (0)
514 #define AUDIO_MODE_SPDIF_MODE (0x1 << 8)
515 #define AUDIO_MODE_MASTER_MODE (0x0 << 8)
516 #define MASTER_VIDEO_INTERLACE_EN (0x1 << 4)
517 #define VIDEO_MASTER_CLK_SEL (0x1 << 2)
518 #define VIDEO_MASTER_MODE_EN (0x1 << 1)
519 #define VIDEO_MODE_MASK (0x1 << 0)
520 #define VIDEO_MODE_SLAVE_MODE (0x1 << 0)
521 #define VIDEO_MODE_MASTER_MODE (0x0 << 0)
524 #define VIDEO_EN (0x1 << 7)
525 #define HDCP_VIDEO_MUTE (0x1 << 6)
528 #define IN_D_RANGE_MASK (0x1 << 7)
530 #define IN_D_RANGE_CEA (0x1 << 7)
531 #define IN_D_RANGE_VESA (0x0 << 7)
532 #define IN_BPC_MASK (0x7 << 4)
534 #define IN_BPC_12_BITS (0x3 << 4)
535 #define IN_BPC_10_BITS (0x2 << 4)
536 #define IN_BPC_8_BITS (0x1 << 4)
537 #define IN_BPC_6_BITS (0x0 << 4)
538 #define IN_COLOR_F_MASK (0x3 << 0)
539 #define IN_COLOR_F_SHIFT (0)
540 #define IN_COLOR_F_YCBCR444 (0x2 << 0)
541 #define IN_COLOR_F_YCBCR422 (0x1 << 0)
542 #define IN_COLOR_F_RGB (0x0 << 0)
545 #define IN_YC_COEFFI_MASK (0x1 << 7)
547 #define IN_YC_COEFFI_ITU709 (0x1 << 7)
548 #define IN_YC_COEFFI_ITU601 (0x0 << 7)
549 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
551 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
552 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
555 #define TEST_PATTERN_GEN_EN (0x1 << 0)
556 #define TEST_PATTERN_GEN_DIS (0x0 << 0)
559 #define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0)
560 #define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0)
561 #define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0)
564 #define BIST_EN (0x1 << 3)
565 #define BIST_WIDTH_MASK (0x1 << 2)
566 #define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2)
567 #define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2)
568 #define BIST_TYPE_MASK (0x3 << 0)
569 #define BIST_TYPE_COLOR_BAR (0x0 << 0)
570 #define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0)
571 #define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0)
574 #define DET_STA (0x1 << 2)
575 #define FORCE_DET (0x1 << 1)
576 #define DET_CTRL (0x1 << 0)
579 #define CHA_CRI(x) (((x) & 0xf) << 4)
580 #define CHA_STA (0x1 << 2)
581 #define FORCE_CHA (0x1 << 1)
582 #define CHA_CTRL (0x1 << 0)
585 #define HPD_STATUS (0x1 << 6)
586 #define F_HPD (0x1 << 5)
587 #define HPD_CTRL (0x1 << 4)
588 #define HDCP_RDY (0x1 << 3)
589 #define STRM_VALID (0x1 << 2)
590 #define F_VALID (0x1 << 1)
591 #define VALID_CTRL (0x1 << 0)
594 #define FIX_M_AUD (0x1 << 4)
595 #define ENHANCED (0x1 << 3)
596 #define FIX_M_VID (0x1 << 2)
597 #define M_VID_UPDATE_CTRL (0x3 << 0)
600 #define M_VID0_CFG(x) ((x) & 0xff)
601 #define M_VID1_CFG(x) (((x) >> 8) & 0xff)
602 #define M_VID2_CFG(x) (((x) >> 16) & 0xff)
605 #define N_VID0_CFG(x) ((x) & 0xff)
606 #define N_VID1_CFG(x) (((x) >> 8) & 0xff)
607 #define N_VID2_CFG(x) (((x) >> 16) & 0xff)
610 #define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
611 #define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
612 #define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
613 #define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
614 #define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
617 #define DPCD_DPCD_REV (0x0000)
618 #define DPCD_MAX_LINK_RATE (0x0001)
619 #define DPCD_MAX_LANE_COUNT (0x0002)
620 #define DPCD_LINK_BW_SET (0x0100)
621 #define DPCD_LANE_COUNT_SET (0x0101)
622 #define DPCD_TRAINING_PATTERN_SET (0x0102)
623 #define DPCD_TRAINING_LANE0_SET (0x0103)
624 #define DPCD_LANE0_1_STATUS (0x0202)
625 #define DPCD_LN_ALIGN_UPDATED (0x0204)
626 #define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
627 #define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
628 #define DPCD_TEST_REQUEST (0x0218)
629 #define DPCD_TEST_RESPONSE (0x0260)
630 #define DPCD_TEST_EDID_CHECKSUM (0x0261)
631 #define DPCD_SINK_POWER_STATE (0x0600)
634 #define DPCD_TEST_EDID_READ (0x1 << 2)
637 #define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
640 #define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
641 #define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
644 #define I2C_EDID_DEVICE_ADDR (0x50)
645 #define I2C_E_EDID_DEVICE_ADDR (0x30)
646 #define EDID_BLOCK_LENGTH (0x80)
647 #define EDID_HEADER_PATTERN (0x00)
648 #define EDID_EXTENSION_FLAG (0x7e)
649 #define EDID_CHECKSUM (0x7f)
652 #define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6)
653 #define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5)
654 #define DPCD_LANE1_CR_DONE (0x1 << 4)
655 #define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2)
656 #define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1)
657 #define DPCD_LANE0_CR_DONE (0x1 << 0)
660 #define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6)
661 #define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3)
662 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6)
663 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6)
664 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6)
665 #define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6)
666 #define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4)
667 #define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3)
668 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4)
669 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4)
670 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4)
671 #define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4)
672 #define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2)
673 #define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3)
674 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2)
675 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2)
676 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2)
677 #define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2)
678 #define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0)
679 #define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3)
680 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0)
681 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0)
682 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0)
683 #define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0)
686 #define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6)
687 #define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3)
688 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6)
689 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6)
690 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6)
691 #define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6)
692 #define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4)
693 #define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3)
694 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4)
695 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4)
696 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4)
697 #define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4)
698 #define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2)
699 #define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3)
700 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2)
701 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2)
702 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2)
703 #define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2)
704 #define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0)
705 #define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3)
706 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0)
707 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0)
708 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0)
709 #define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0)
712 #define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
713 #define DPCD_LN_COUNT_SET(x) ((x) & 0x1f)
716 #define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
717 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
718 #define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
721 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3)
722 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3)
723 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3)
724 #define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3)
725 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0)
726 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0)
727 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0)
728 #define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0)
730 #define DPCD_REQ_ADJ_SWING (0x00)
731 #define DPCD_REQ_ADJ_EMPHASIS (0x01)
733 #define DP_LANE_STAT_CR_DONE (0x01 << 0)
734 #define DP_LANE_STAT_CE_DONE (0x01 << 1)
735 #define DP_LANE_STAT_SYM_LOCK (0x01 << 2)