Lines Matching +full:sel +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clk.h>
32 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
33 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
34 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
35 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
36 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0},
37 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0},
38 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0},
39 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0},
40 {PERIPH_ID_I2C4, -1, 0x7, 0x7, -1, 24, 0},
41 {PERIPH_ID_I2C5, -1, 0x7, 0x7, -1, 24, 0},
42 {PERIPH_ID_I2C6, -1, 0x7, 0x7, -1, 24, 0},
43 {PERIPH_ID_I2C7, -1, 0x7, 0x7, -1, 24, 0},
56 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 0, -1},
57 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 0, -1},
58 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 0, -1},
59 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 0, -1},
60 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 0, -1},
62 {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
67 {PERIPH_ID_UART0, 0xf, 0xf, -1, 4, 8, -1},
68 {PERIPH_ID_UART1, 0xf, 0xf, -1, 8, 12, -1},
69 {PERIPH_ID_UART2, 0xf, 0xf, -1, 12, 16, -1},
70 {PERIPH_ID_UART3, 0xf, 0xf, -1, 16, 20, -1},
71 {PERIPH_ID_I2C0, -1, 0x3f, -1, -1, 8, -1},
72 {PERIPH_ID_I2C1, -1, 0x3f, -1, -1, 8, -1},
73 {PERIPH_ID_I2C2, -1, 0x3f, -1, -1, 8, -1},
74 {PERIPH_ID_I2C3, -1, 0x3f, -1, -1, 8, -1},
75 {PERIPH_ID_I2C4, -1, 0x3f, -1, -1, 8, -1},
76 {PERIPH_ID_I2C5, -1, 0x3f, -1, -1, 8, -1},
77 {PERIPH_ID_I2C6, -1, 0x3f, -1, -1, 8, -1},
78 {PERIPH_ID_I2C7, -1, 0x3f, -1, -1, 8, -1},
82 {PERIPH_ID_SDMMC0, 0x7, 0x3ff, -1, 8, 0, -1},
83 {PERIPH_ID_SDMMC1, 0x7, 0x3ff, -1, 12, 10, -1},
84 {PERIPH_ID_SDMMC2, 0x7, 0x3ff, -1, 16, 20, -1},
85 {PERIPH_ID_I2C8, -1, 0x3f, -1, -1, 8, -1},
86 {PERIPH_ID_I2C9, -1, 0x3f, -1, -1, 8, -1},
91 {PERIPH_ID_PWM0, 0xf, 0xf, -1, 24, 28, -1},
92 {PERIPH_ID_PWM1, 0xf, 0xf, -1, 24, 28, -1},
93 {PERIPH_ID_PWM2, 0xf, 0xf, -1, 24, 28, -1},
94 {PERIPH_ID_PWM3, 0xf, 0xf, -1, 24, 28, -1},
95 {PERIPH_ID_PWM4, 0xf, 0xf, -1, 24, 28, -1},
96 {PERIPH_ID_I2C10, -1, 0x3f, -1, -1, 8, -1},
98 {PERIPH_ID_NONE, -1, -1, -1, -1, -1, -1},
174 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1)) in exynos_get_pll_clk()
177 fout = m * (freq / (p * (1 << (s - 1)))); in exynos_get_pll_clk()
187 struct exynos4_clock *clk = in exynos4_get_pll_clk() local
193 r = readl(&clk->apll_con0); in exynos4_get_pll_clk()
196 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
199 r = readl(&clk->epll_con0); in exynos4_get_pll_clk()
200 k = readl(&clk->epll_con1); in exynos4_get_pll_clk()
203 r = readl(&clk->vpll_con0); in exynos4_get_pll_clk()
204 k = readl(&clk->vpll_con1); in exynos4_get_pll_clk()
217 struct exynos4x12_clock *clk = in exynos4x12_get_pll_clk() local
223 r = readl(&clk->apll_con0); in exynos4x12_get_pll_clk()
226 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
229 r = readl(&clk->epll_con0); in exynos4x12_get_pll_clk()
230 k = readl(&clk->epll_con1); in exynos4x12_get_pll_clk()
233 r = readl(&clk->vpll_con0); in exynos4x12_get_pll_clk()
234 k = readl(&clk->vpll_con1); in exynos4x12_get_pll_clk()
247 struct exynos5_clock *clk = in exynos5_get_pll_clk() local
254 r = readl(&clk->apll_con0); in exynos5_get_pll_clk()
257 r = readl(&clk->mpll_con0); in exynos5_get_pll_clk()
260 r = readl(&clk->epll_con0); in exynos5_get_pll_clk()
261 k = readl(&clk->epll_con1); in exynos5_get_pll_clk()
264 r = readl(&clk->vpll_con0); in exynos5_get_pll_clk()
265 k = readl(&clk->vpll_con1); in exynos5_get_pll_clk()
268 r = readl(&clk->bpll_con0); in exynos5_get_pll_clk()
280 pll_div2_sel = readl(&clk->pll_div2_sel); in exynos5_get_pll_clk()
292 fout_sel = -1; in exynos5_get_pll_clk()
306 struct exynos5420_clock *clk = in exynos542x_get_pll_clk() local
312 r = readl(&clk->apll_con0); in exynos542x_get_pll_clk()
315 r = readl(&clk->mpll_con0); in exynos542x_get_pll_clk()
318 r = readl(&clk->epll_con0); in exynos542x_get_pll_clk()
319 k = readl(&clk->epll_con1); in exynos542x_get_pll_clk()
322 r = readl(&clk->vpll_con0); in exynos542x_get_pll_clk()
323 k = readl(&clk->vpll_con1); in exynos542x_get_pll_clk()
326 r = readl(&clk->bpll_con0); in exynos542x_get_pll_clk()
329 r = readl(&clk->rpll_con0); in exynos542x_get_pll_clk()
330 k = readl(&clk->rpll_con1); in exynos542x_get_pll_clk()
333 r = readl(&clk->spll_con0); in exynos542x_get_pll_clk()
369 struct exynos5_clock *clk = in exynos5_get_periph_rate() local
377 src = readl(&clk->src_peric0); in exynos5_get_periph_rate()
378 div = readl(&clk->div_peric0); in exynos5_get_periph_rate()
385 src = readl(&clk->src_peric0); in exynos5_get_periph_rate()
386 div = readl(&clk->div_peric3); in exynos5_get_periph_rate()
389 src = readl(&clk->src_mau); in exynos5_get_periph_rate()
390 div = sub_div = readl(&clk->div_mau); in exynos5_get_periph_rate()
393 src = readl(&clk->src_peric1); in exynos5_get_periph_rate()
394 div = sub_div = readl(&clk->div_peric1); in exynos5_get_periph_rate()
397 src = readl(&clk->src_peric1); in exynos5_get_periph_rate()
398 div = sub_div = readl(&clk->div_peric2); in exynos5_get_periph_rate()
402 src = readl(&clk->sclk_src_isp); in exynos5_get_periph_rate()
403 div = sub_div = readl(&clk->sclk_div_isp); in exynos5_get_periph_rate()
407 src = readl(&clk->src_fsys); in exynos5_get_periph_rate()
408 div = sub_div = readl(&clk->div_fsys1); in exynos5_get_periph_rate()
412 src = readl(&clk->src_fsys); in exynos5_get_periph_rate()
413 div = sub_div = readl(&clk->div_fsys2); in exynos5_get_periph_rate()
424 div = readl(&clk->div_top1); in exynos5_get_periph_rate()
425 sub_div = readl(&clk->div_top0); in exynos5_get_periph_rate()
429 return -1; in exynos5_get_periph_rate()
432 if (bit_info->src_bit >= 0) in exynos5_get_periph_rate()
433 src = (src >> bit_info->src_bit) & bit_info->src_mask; in exynos5_get_periph_rate()
451 if (bit_info->div_bit >= 0) in exynos5_get_periph_rate()
452 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos5_get_periph_rate()
454 /* Clock pre-divider ratio for this peripheral */ in exynos5_get_periph_rate()
455 if (bit_info->prediv_bit >= 0) in exynos5_get_periph_rate()
456 sub_div = (sub_div >> bit_info->prediv_bit) in exynos5_get_periph_rate()
457 & bit_info->prediv_mask; in exynos5_get_periph_rate()
468 struct exynos5420_clock *clk = in exynos542x_get_periph_rate() local
481 src = readl(&clk->src_peric0); in exynos542x_get_periph_rate()
482 div = readl(&clk->div_peric0); in exynos542x_get_periph_rate()
487 src = readl(&clk->src_peric1); in exynos542x_get_periph_rate()
488 div = readl(&clk->div_peric1); in exynos542x_get_periph_rate()
489 sub_div = readl(&clk->div_peric4); in exynos542x_get_periph_rate()
493 src = readl(&clk->src_isp); in exynos542x_get_periph_rate()
494 div = readl(&clk->div_isp1); in exynos542x_get_periph_rate()
495 sub_div = readl(&clk->div_isp1); in exynos542x_get_periph_rate()
501 src = readl(&clk->src_fsys); in exynos542x_get_periph_rate()
502 div = readl(&clk->div_fsys1); in exynos542x_get_periph_rate()
516 div = readl(&clk->div_top1); in exynos542x_get_periph_rate()
520 return -1; in exynos542x_get_periph_rate()
523 if (bit_info->src_bit >= 0) in exynos542x_get_periph_rate()
524 src = (src >> bit_info->src_bit) & bit_info->src_mask; in exynos542x_get_periph_rate()
545 if (bit_info->div_bit >= 0) in exynos542x_get_periph_rate()
546 div = (div >> bit_info->div_bit) & bit_info->div_mask; in exynos542x_get_periph_rate()
548 /* Clock pre-divider ratio for this peripheral */ in exynos542x_get_periph_rate()
549 if (bit_info->prediv_bit >= 0) in exynos542x_get_periph_rate()
550 sub_div = (sub_div >> bit_info->prediv_bit) in exynos542x_get_periph_rate()
551 & bit_info->prediv_mask; in exynos542x_get_periph_rate()
571 struct exynos4_clock *clk = in exynos4_get_arm_clk() local
578 div = readl(&clk->div_cpu0); in exynos4_get_arm_clk()
593 struct exynos4x12_clock *clk = in exynos4x12_get_arm_clk() local
600 div = readl(&clk->div_cpu0); in exynos4x12_get_arm_clk()
615 struct exynos5_clock *clk = in exynos5_get_arm_clk() local
622 div = readl(&clk->div_cpu0); in exynos5_get_arm_clk()
637 struct exynos4_clock *clk = in exynos4_get_pwm_clk() local
640 unsigned int sel; in exynos4_get_pwm_clk() local
648 sel = readl(&clk->src_peril0); in exynos4_get_pwm_clk()
649 sel = (sel >> 24) & 0xf; in exynos4_get_pwm_clk()
651 if (sel == 0x6) in exynos4_get_pwm_clk()
653 else if (sel == 0x7) in exynos4_get_pwm_clk()
655 else if (sel == 0x8) in exynos4_get_pwm_clk()
664 ratio = readl(&clk->div_peril3); in exynos4_get_pwm_clk()
694 struct exynos4_clock *clk = in exynos4_get_uart_clk() local
697 unsigned int sel; in exynos4_get_uart_clk() local
709 sel = readl(&clk->src_peril0); in exynos4_get_uart_clk()
710 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_uart_clk()
712 if (sel == 0x6) in exynos4_get_uart_clk()
714 else if (sel == 0x7) in exynos4_get_uart_clk()
716 else if (sel == 0x8) in exynos4_get_uart_clk()
730 ratio = readl(&clk->div_peril0); in exynos4_get_uart_clk()
741 struct exynos4x12_clock *clk = in exynos4x12_get_uart_clk() local
744 unsigned int sel; in exynos4x12_get_uart_clk() local
755 sel = readl(&clk->src_peril0); in exynos4x12_get_uart_clk()
756 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4x12_get_uart_clk()
758 if (sel == 0x6) in exynos4x12_get_uart_clk()
760 else if (sel == 0x7) in exynos4x12_get_uart_clk()
762 else if (sel == 0x8) in exynos4x12_get_uart_clk()
775 ratio = readl(&clk->div_peril0); in exynos4x12_get_uart_clk()
785 struct exynos4_clock *clk = in exynos4_get_mmc_clk() local
788 unsigned int sel, ratio, pre_ratio; in exynos4_get_mmc_clk() local
791 sel = readl(&clk->src_fsys); in exynos4_get_mmc_clk()
792 sel = (sel >> (dev_index << 2)) & 0xf; in exynos4_get_mmc_clk()
794 if (sel == 0x6) in exynos4_get_mmc_clk()
796 else if (sel == 0x7) in exynos4_get_mmc_clk()
798 else if (sel == 0x8) in exynos4_get_mmc_clk()
806 ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()
807 pre_ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()
811 ratio = readl(&clk->div_fsys2); in exynos4_get_mmc_clk()
812 pre_ratio = readl(&clk->div_fsys2); in exynos4_get_mmc_clk()
815 ratio = readl(&clk->div_fsys3); in exynos4_get_mmc_clk()
816 pre_ratio = readl(&clk->div_fsys3); in exynos4_get_mmc_clk()
835 struct exynos4_clock *clk = in exynos4_set_mmc_clk() local
848 addr = (unsigned int)&clk->div_fsys1; in exynos4_set_mmc_clk()
852 addr = (unsigned int)&clk->div_fsys3; in exynos4_set_mmc_clk()
853 dev_index -= 4; in exynos4_set_mmc_clk()
858 addr = (unsigned int)&clk->div_fsys2; in exynos4_set_mmc_clk()
859 dev_index -= 2; in exynos4_set_mmc_clk()
870 struct exynos5_clock *clk = in exynos5_set_mmc_clk() local
881 addr = (unsigned int)&clk->div_fsys1; in exynos5_set_mmc_clk()
883 addr = (unsigned int)&clk->div_fsys2; in exynos5_set_mmc_clk()
884 dev_index -= 2; in exynos5_set_mmc_clk()
894 struct exynos5420_clock *clk = in exynos5420_set_mmc_clk() local
905 addr = (unsigned int)&clk->div_fsys1; in exynos5420_set_mmc_clk()
914 struct exynos4_clock *clk = in exynos4_get_lcd_clk() local
917 unsigned int sel; in exynos4_get_lcd_clk() local
924 sel = readl(&clk->src_lcd0); in exynos4_get_lcd_clk()
925 sel = sel & 0xf; in exynos4_get_lcd_clk()
932 if (sel == 0x6) in exynos4_get_lcd_clk()
934 else if (sel == 0x7) in exynos4_get_lcd_clk()
936 else if (sel == 0x8) in exynos4_get_lcd_clk()
945 ratio = readl(&clk->div_lcd0); in exynos4_get_lcd_clk()
956 struct exynos5_clock *clk = in exynos5_get_lcd_clk() local
959 unsigned int sel; in exynos5_get_lcd_clk() local
966 sel = readl(&clk->src_disp1_0); in exynos5_get_lcd_clk()
967 sel = sel & 0xf; in exynos5_get_lcd_clk()
974 if (sel == 0x6) in exynos5_get_lcd_clk()
976 else if (sel == 0x7) in exynos5_get_lcd_clk()
978 else if (sel == 0x8) in exynos5_get_lcd_clk()
987 ratio = readl(&clk->div_disp1_0); in exynos5_get_lcd_clk()
997 struct exynos5420_clock *clk = in exynos5420_get_lcd_clk() local
1000 unsigned int sel; in exynos5420_get_lcd_clk() local
1009 sel = readl(&clk->src_disp10); in exynos5420_get_lcd_clk()
1010 sel &= (1 << 4); in exynos5420_get_lcd_clk()
1012 if (sel) in exynos5420_get_lcd_clk()
1021 ratio = readl(&clk->div_disp10); in exynos5420_get_lcd_clk()
1031 struct exynos5420_clock *clk = in exynos5800_get_lcd_clk() local
1034 unsigned int sel; in exynos5800_get_lcd_clk() local
1041 sel = (readl(&clk->src_disp10) >> 4) & 0x7; in exynos5800_get_lcd_clk()
1043 if (sel) { in exynos5800_get_lcd_clk()
1051 sclk = get_pll_clk(reg_map[sel]); in exynos5800_get_lcd_clk()
1058 ratio = readl(&clk->div_disp10) & 0xf; in exynos5800_get_lcd_clk()
1065 struct exynos4_clock *clk = in exynos4_set_lcd_clk() local
1078 setbits_le32(&clk->gate_block, 1 << 4); in exynos4_set_lcd_clk()
1088 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6); in exynos4_set_lcd_clk()
1100 setbits_le32(&clk->gate_ip_lcd0, 1 << 0); in exynos4_set_lcd_clk()
1112 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1); in exynos4_set_lcd_clk()
1117 struct exynos5_clock *clk = in exynos5_set_lcd_clk() local
1130 setbits_le32(&clk->gate_block, 1 << 4); in exynos5_set_lcd_clk()
1140 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6); in exynos5_set_lcd_clk()
1152 setbits_le32(&clk->gate_ip_disp1, 1 << 0); in exynos5_set_lcd_clk()
1164 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0); in exynos5_set_lcd_clk()
1169 struct exynos5420_clock *clk = in exynos5420_set_lcd_clk() local
1179 cfg = readl(&clk->src_disp10); in exynos5420_set_lcd_clk()
1182 writel(cfg, &clk->src_disp10); in exynos5420_set_lcd_clk()
1188 cfg = readl(&clk->div_disp10); in exynos5420_set_lcd_clk()
1191 writel(cfg, &clk->div_disp10); in exynos5420_set_lcd_clk()
1196 struct exynos5420_clock *clk = in exynos5800_set_lcd_clk() local
1206 cfg = readl(&clk->src_disp10) | (0x7 << 4); in exynos5800_set_lcd_clk()
1207 writel(cfg, &clk->src_disp10); in exynos5800_set_lcd_clk()
1213 clrsetbits_le32(&clk->div_disp10, 0xf << 0, 0x0 << 0); in exynos5800_set_lcd_clk()
1218 struct exynos4_clock *clk = in exynos4_set_mipi_clk() local
1229 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12); in exynos4_set_mipi_clk()
1239 setbits_le32(&clk->src_mask_lcd0, 0x1 << 12); in exynos4_set_mipi_clk()
1251 setbits_le32(&clk->gate_ip_lcd0, 1 << 3); in exynos4_set_mipi_clk()
1263 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16); in exynos4_set_mipi_clk()
1272 struct exynos5_clock *clk = in exynos5_set_epll_clk() local
1275 epll_con = readl(&clk->epll_con0); in exynos5_set_epll_clk()
1288 return -1; in exynos5_set_epll_clk()
1304 writel(lockcnt, &clk->epll_lock); in exynos5_set_epll_clk()
1305 writel(epll_con, &clk->epll_con0); in exynos5_set_epll_clk()
1306 writel(epll_con_k, &clk->epll_con1); in exynos5_set_epll_clk()
1310 while (!(readl(&clk->epll_con0) & in exynos5_set_epll_clk()
1314 return -1; in exynos5_set_epll_clk()
1322 struct exynos5420_clock *clk = in exynos5420_set_i2s_clk_source() local
1325 setbits_le32(&clk->src_top6, EXYNOS5420_CLK_SRC_MOUT_EPLL); in exynos5420_set_i2s_clk_source()
1326 clrsetbits_le32(&clk->src_mau, EXYNOS5420_AUDIO0_SEL_MASK, in exynos5420_set_i2s_clk_source()
1335 struct exynos5_clock *clk = in exynos5_set_i2s_clk_source() local
1340 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL); in exynos5_set_i2s_clk_source()
1341 clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK, in exynos5_set_i2s_clk_source()
1345 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, in exynos5_set_i2s_clk_source()
1348 return -1; in exynos5_set_i2s_clk_source()
1357 struct exynos5_clock *clk = in exynos5_set_i2s_clk_prescaler() local
1364 return -1; in exynos5_set_i2s_clk_prescaler()
1373 return -1; in exynos5_set_i2s_clk_prescaler()
1375 clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK, in exynos5_set_i2s_clk_prescaler()
1382 return -1; in exynos5_set_i2s_clk_prescaler()
1384 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, in exynos5_set_i2s_clk_prescaler()
1387 return -1; in exynos5_set_i2s_clk_prescaler()
1404 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1412 int best_main_scalar = -1; in clock_calc_best_scalar()
1414 const unsigned int cap = (1 << fine_scalar_bits) - 1; in clock_calc_best_scalar()
1426 return -1; in clock_calc_best_scalar()
1436 const int error = target_rate - effective_rate; in clock_calc_best_scalar()
1454 struct exynos5_clock *clk = in exynos5_set_spi_clk() local
1466 return -1; in exynos5_set_spi_clk()
1468 main = main - 1; in exynos5_set_spi_clk()
1469 fine = fine - 1; in exynos5_set_spi_clk()
1473 reg = &clk->div_peric1; in exynos5_set_spi_clk()
1478 reg = &clk->div_peric1; in exynos5_set_spi_clk()
1483 reg = &clk->div_peric2; in exynos5_set_spi_clk()
1488 reg = &clk->sclk_div_isp; in exynos5_set_spi_clk()
1493 reg = &clk->sclk_div_isp; in exynos5_set_spi_clk()
1500 return -1; in exynos5_set_spi_clk()
1511 struct exynos5420_clock *clk = in exynos5420_set_spi_clk() local
1524 return -1; in exynos5420_set_spi_clk()
1526 main = main - 1; in exynos5420_set_spi_clk()
1527 fine = fine - 1; in exynos5420_set_spi_clk()
1531 reg = &clk->div_peric1; in exynos5420_set_spi_clk()
1533 pre_reg = &clk->div_peric4; in exynos5420_set_spi_clk()
1537 reg = &clk->div_peric1; in exynos5420_set_spi_clk()
1539 pre_reg = &clk->div_peric4; in exynos5420_set_spi_clk()
1543 reg = &clk->div_peric1; in exynos5420_set_spi_clk()
1545 pre_reg = &clk->div_peric4; in exynos5420_set_spi_clk()
1549 reg = &clk->div_isp1; in exynos5420_set_spi_clk()
1551 pre_reg = &clk->div_isp1; in exynos5420_set_spi_clk()
1555 reg = &clk->div_isp1; in exynos5420_set_spi_clk()
1557 pre_reg = &clk->div_isp1; in exynos5420_set_spi_clk()
1563 return -1; in exynos5420_set_spi_clk()
1575 struct exynos4_clock *clk = in exynos4_get_i2c_clk() local
1582 ratio = (readl(&clk->div_top)) >> 4; in exynos4_get_i2c_clk()
1658 return -1; in get_uart_clk()
1694 return -1; in get_mmc_clk()
1704 div -= 1; in set_mmc_clk()