Lines Matching +full:0 +full:xfffffe50
18 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
30 #define ATMEL_ID_USART0 12 /* USART 0 */
36 #define ATMEL_ID_TWI0 18 /* Two-Wire Interface 0 */
39 #define ATMEL_ID_MCI0 21 /* High Speed Multimedia Card Interface 0 */
42 #define ATMEL_ID_SPI0 24 /* Serial Peripheral Interface 0 */
56 #define ATMEL_ID_SSC0 38 /* Synchronous Serial Controller 0 */
70 #define ARCH_ID_SAMA5D3 0x8a5c07c0
71 #define ARCH_EXID_SAMA5D31 0x00444300
72 #define ARCH_EXID_SAMA5D33 0x00414300
73 #define ARCH_EXID_SAMA5D34 0x00414301
74 #define ARCH_EXID_SAMA5D35 0x00584300
75 #define ARCH_EXID_SAMA5D36 0x00004301
92 #define ATMEL_BASE_MCI0 0xf0000000
93 #define ATMEL_BASE_SPI0 0xf0004000
94 #define ATMEL_BASE_SSC0 0xf000C000
95 #define ATMEL_BASE_TC2 0xf0010000
96 #define ATMEL_BASE_TWI0 0xf0014000
97 #define ATMEL_BASE_TWI1 0xf0018000
98 #define ATMEL_BASE_USART0 0xf001c000
99 #define ATMEL_BASE_USART1 0xf0020000
100 #define ATMEL_BASE_UART0 0xf0024000
101 #define ATMEL_BASE_GMAC 0xf0028000
102 #define ATMEL_BASE_PWMC 0xf002c000
103 #define ATMEL_BASE_LCDC 0xf0030000
104 #define ATMEL_BASE_ISI 0xf0034000
105 #define ATMEL_BASE_SFR 0xf0038000
106 /* Reserved: 0xf003c000 - 0xf8000000 */
107 #define ATMEL_BASE_MCI1 0xf8000000
108 #define ATMEL_BASE_MCI2 0xf8004000
109 #define ATMEL_BASE_SPI1 0xf8008000
110 #define ATMEL_BASE_SSC1 0xf800c000
111 #define ATMEL_BASE_CAN1 0xf8010000
112 #define ATMEL_BASE_TC3 0xf8014000
113 #define ATMEL_BASE_TSADC 0xf8018000
114 #define ATMEL_BASE_TWI2 0xf801c000
115 #define ATMEL_BASE_USART2 0xf8020000
116 #define ATMEL_BASE_USART3 0xf8024000
117 #define ATMEL_BASE_UART1 0xf8028000
118 #define ATMEL_BASE_EMAC 0xf802c000
119 #define ATMEL_BASE_UDPHS 0xf8030000
120 #define ATMEL_BASE_SHA 0xf8034000
121 #define ATMEL_BASE_AES 0xf8038000
122 #define ATMEL_BASE_TDES 0xf803c000
123 #define ATMEL_BASE_TRNG 0xf8040000
124 /* Reserved: 0xf804400 - 0xffffc00 */
129 #define ATMEL_BASE_SYS 0xffffc000
130 #define ATMEL_BASE_SMC 0xffffc000
131 #define ATMEL_BASE_PMECC (ATMEL_BASE_SMC + 0x070)
132 #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_SMC + 0x500)
133 #define ATMEL_BASE_FUSE 0xffffe400
134 #define ATMEL_BASE_DMAC0 0xffffe600
135 #define ATMEL_BASE_DMAC1 0xffffe800
136 #define ATMEL_BASE_MPDDRC 0xffffea00
137 #define ATMEL_BASE_MATRIX 0xffffec00
138 #define ATMEL_BASE_DBGU 0xffffee00
139 #define ATMEL_BASE_AIC 0xfffff000
140 #define ATMEL_BASE_PIOA 0xfffff200
141 #define ATMEL_BASE_PIOB 0xfffff400
142 #define ATMEL_BASE_PIOC 0xfffff600
143 #define ATMEL_BASE_PIOD 0xfffff800
144 #define ATMEL_BASE_PIOE 0xfffffa00
145 #define ATMEL_BASE_PMC 0xfffffc00
146 #define ATMEL_BASE_RSTC 0xfffffe00
147 #define ATMEL_BASE_SHDWN 0xfffffe10
148 #define ATMEL_BASE_PIT 0xfffffe30
149 #define ATMEL_BASE_WDT 0xfffffe40
150 #define ATMEL_BASE_SCKCR 0xfffffe50
151 #define ATMEL_BASE_GPBR 0xfffffe60
152 #define ATMEL_BASE_RTC 0xfffffeb0
153 /* Reserved: 0xfffffee0 - 0xffffffff */
155 #define ATMEL_CHIPID_CIDR 0xffffee40
156 #define ATMEL_CHIPID_EXID 0xffffee44
161 #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
162 #define ATMEL_BASE_SRAM 0x00200000 /* Internal ROM base address */
163 #define ATMEL_BASE_SRAM0 0x00300000 /* Internal SRAM base address */
164 #define ATMEL_BASE_SRAM1 0x00310000 /* Internal SRAM base address */
165 #define ATMEL_BASE_SMD 0x00400000 /* Internal ROM base address */
166 #define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
167 #define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
168 #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
169 #define ATMEL_BASE_AXI 0x00800000 /* Video Decoder Controller */
170 #define ATMEL_BASE_DAP 0x00900000 /* Video Decoder Controller */
175 #define ATMEL_BASE_CS0 0x10000000
176 #define ATMEL_BASE_DDRCS 0x20000000
177 #define ATMEL_BASE_CS1 0x40000000
178 #define ATMEL_BASE_CS2 0x50000000
179 #define ATMEL_BASE_CS3 0x60000000
188 #define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
193 #define ATMEL_PMECC_INDEX_OFFSET_512 0x10000
194 #define ATMEL_PMECC_INDEX_OFFSET_1024 0x18000