Lines Matching +full:0 +full:x00000053
15 #define ATMEL_ID_FIQ 0 /* FIQ Interrupt ID */
21 #define ATMEL_ID_XDMAC0 6 /* DMA Controller 0 */
44 #define ATMEL_ID_TWIHS0 29 /* Two-wire Interface 0 */
46 #define ATMEL_ID_SDMMC0 31 /* Secure Data Memory Card Controller 0 */
48 #define ATMEL_ID_SPI0 33 /* Serial Peripheral Interface 0 */
50 #define ATMEL_ID_TC0 35 /* Timer Counter 0 (ch.0,1,2) */
53 #define ATMEL_ID_PWM 38 /* PWMController0 (ch. 0,1,2,3) */
58 #define ATMEL_ID_SSC0 43 /* Serial Synchronous Controller 0 */
69 #define ATMEL_ID_I2SC0 54 /* Inter-IC Sound Controller 0 */
71 #define ATMEL_ID_CAN0_INT0 56 /* MCAN 0 Interrupt0 */
79 #define ATMEL_ID_CAN0_INT1 64 /* MCAN 0 Interrupt1 */
86 #define ATMEL_ID_SDMMC0_TIMER 71 /* Secure Data Memory Card Controller 0 (TIMER) */
98 #define ATMEL_BASE_LCDC 0xf0000000
99 #define ATMEL_BASE_XDMAC1 0xf0004000
100 #define ATMEL_BASE_MPDDRC 0xf000c000
101 #define ATMEL_BASE_XDMAC0 0xf0010000
102 #define ATMEL_BASE_PMC 0xf0014000
103 #define ATMEL_BASE_MATRIX0 0xf0018000
104 #define ATMEL_BASE_QSPI0 0xf0020000
105 #define ATMEL_BASE_QSPI1 0xf0024000
106 #define ATMEL_BASE_SPI0 0xf8000000
107 #define ATMEL_BASE_GMAC 0xf8008000
108 #define ATMEL_BASE_TC0 0xf800c000
109 #define ATMEL_BASE_TC1 0xf8010000
110 #define ATMEL_BASE_HSMC 0xf8014000
111 #define ATMEL_BASE_UART0 0xf801c000
112 #define ATMEL_BASE_UART1 0xf8020000
113 #define ATMEL_BASE_UART2 0xf8024000
114 #define ATMEL_BASE_TWI0 0xf8028000
115 #define ATMEL_BASE_SFR 0xf8030000
116 #define ATMEL_BASE_SYSC 0xf8048000
117 #define ATMEL_BASE_SPI1 0xfc000000
118 #define ATMEL_BASE_UART3 0xfc008000
119 #define ATMEL_BASE_UART4 0xfc00c000
120 #define ATMEL_BASE_TWI1 0xfc028000
121 #define ATMEL_BASE_UDPHS 0xfc02c000
123 #define ATMEL_BASE_PIOA 0xfc038000
124 #define ATMEL_BASE_MATRIX1 0xfc03c000
126 #define ATMEL_CHIPID_CIDR 0xfc069000
127 #define ATMEL_CHIPID_EXID 0xfc069004
132 #define ATMEL_BASE_CS0 0x10000000
133 #define ATMEL_BASE_DDRCS 0x20000000
134 #define ATMEL_BASE_CS1 0x60000000
135 #define ATMEL_BASE_CS2 0x70000000
136 #define ATMEL_BASE_CS3 0x80000000
137 #define ATMEL_BASE_QSPI0_AES_MEM 0x90000000
138 #define ATMEL_BASE_QSPI1_AES_MEM 0x98000000
139 #define ATMEL_BASE_SDMMC0 0xa0000000
140 #define ATMEL_BASE_SDMMC1 0xb0000000
141 #define ATMEL_BASE_QSPI0_MEM 0xd0000000
142 #define ATMEL_BASE_QSPI1_MEM 0xd8000000
147 #define ATMEL_BASE_UDPHS_FIFO 0x00300000 /* USB Device HS controller */
148 #define ATMEL_BASE_OHCI 0x00400000 /* USB Host controller (OHCI) */
149 #define ATMEL_BASE_EHCI 0x00500000 /* USB Host controller (EHCI) */
155 #define ATMEL_BASE_SHDWC (ATMEL_BASE_SYSC + 0x10)
156 #define ATMEL_BASE_PIT (ATMEL_BASE_SYSC + 0x30)
157 #define ATMEL_BASE_WDT (ATMEL_BASE_SYSC + 0x40)
158 #define ATMEL_BASE_SCKC (ATMEL_BASE_SYSC + 0x50)
159 #define ATMEL_BASE_RTC (ATMEL_BASE_SYSC + 0xb0)
164 #define ATMEL_BASE_PMECC (ATMEL_BASE_HSMC + 0x70)
165 #define ATMEL_BASE_PMERRLOC (ATMEL_BASE_HSMC + 0x500)
166 #define ATMEL_BASE_SMC (ATMEL_BASE_HSMC + 0x700)
168 #define ATMEL_BASE_PIOB (ATMEL_BASE_PIOA + 0x40)
169 #define ATMEL_BASE_PIOC (ATMEL_BASE_PIOB + 0x40)
170 #define ATMEL_BASE_PIOD (ATMEL_BASE_PIOC + 0x40)
177 #define ATMEL_SFR_AICREDIR_KEY 0xB6D81C4D
180 #define H64MX_SLAVE_AXIMX_BRIDGE 0 /* Bridge from H64MX to AXIMX */
197 #define H32MX_SLAVE_H64MX_BRIDGE 0 /* Bridge from H32MX to H64MX */
198 #define H32MX_SLAVE_PERIPH_BRIDGE0 1 /* H32MX Peripheral Bridge 0 */
206 #define ARCH_ID_SAMA5D2 0x8a5c08c0
207 #define ARCH_EXID_SAMA5D21CU 0x0000005a
208 #define ARCH_EXID_SAMA5D22CU 0x00000059
209 #define ARCH_EXID_SAMA5D22CN 0x00000069
210 #define ARCH_EXID_SAMA5D23CU 0x00000058
211 #define ARCH_EXID_SAMA5D24CX 0x00000004
212 #define ARCH_EXID_SAMA5D24CU 0x00000014
213 #define ARCH_EXID_SAMA5D26CU 0x00000012
214 #define ARCH_EXID_SAMA5D27CU 0x00000011
215 #define ARCH_EXID_SAMA5D27CN 0x00000021
216 #define ARCH_EXID_SAMA5D28CU 0x00000010
217 #define ARCH_EXID_SAMA5D28CN 0x00000020
219 #define ARCH_ID_SAMA5D2_SIP 0x8a5c08c2
220 #define ARCH_EXID_SAMA5D225C_D1M 0x00000053
221 #define ARCH_EXID_SAMA5D27C_D5M 0x00000032
222 #define ARCH_EXID_SAMA5D27C_D1G 0x00000033
223 #define ARCH_EXID_SAMA5D28C_D1G 0x00000013
226 #define CONFIG_SYS_TIMER_COUNTER 0xf804803c