Lines Matching +full:0 +full:xfffffe00
17 #define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23 #define ATMEL_ID_USART0 5 /* USART 0 */
27 #define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
30 #define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
31 #define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
33 #define ATMEL_ID_UART0 15 /* UART 0 */
35 #define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
38 #define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
53 #define ATMEL_BASE_SPI0 0xf0000000
54 #define ATMEL_BASE_SPI1 0xf0004000
55 #define ATMEL_BASE_HSMCI0 0xf0008000
56 #define ATMEL_BASE_HSMCI1 0xf000c000
57 #define ATMEL_BASE_SSC 0xf0010000
58 #define ATMEL_BASE_CAN0 0xf8000000
59 #define ATMEL_BASE_CAN1 0xf8004000
60 #define ATMEL_BASE_TC0 0xf8008000
61 #define ATMEL_BASE_TC1 0xf8008040
62 #define ATMEL_BASE_TC2 0xf8008080
63 #define ATMEL_BASE_TC3 0xf800c000
64 #define ATMEL_BASE_TC4 0xf800c040
65 #define ATMEL_BASE_TC5 0xf800c080
66 #define ATMEL_BASE_TWI0 0xf8010000
67 #define ATMEL_BASE_TWI1 0xf8014000
68 #define ATMEL_BASE_TWI2 0xf8018000
69 #define ATMEL_BASE_USART0 0xf801c000
70 #define ATMEL_BASE_USART1 0xf8020000
71 #define ATMEL_BASE_USART2 0xf8024000
72 #define ATMEL_BASE_USART3 0xf8028000
73 #define ATMEL_BASE_EMAC0 0xf802c000
74 #define ATMEL_BASE_EMAC1 0xf8030000
75 #define ATMEL_BASE_PWM 0xf8034000
76 #define ATMEL_BASE_LCDC 0xf8038000
77 #define ATMEL_BASE_UDPHS 0xf803c000
78 #define ATMEL_BASE_UART0 0xf8040000
79 #define ATMEL_BASE_UART1 0xf8044000
80 #define ATMEL_BASE_ISI 0xf8048000
81 #define ATMEL_BASE_ADC 0xf804c000
82 #define ATMEL_BASE_SYS 0xffffc000
87 #define ATMEL_BASE_FUSE 0xffffdc00
88 #define ATMEL_BASE_MATRIX 0xffffde00
89 #define ATMEL_BASE_PMECC 0xffffe000
90 #define ATMEL_BASE_PMERRLOC 0xffffe600
91 #define ATMEL_BASE_DDRSDRC 0xffffe800
92 #define ATMEL_BASE_SMC 0xffffea00
93 #define ATMEL_BASE_DMAC0 0xffffec00
94 #define ATMEL_BASE_DMAC1 0xffffee00
95 #define ATMEL_BASE_AIC 0xfffff000
96 #define ATMEL_BASE_DBGU 0xfffff200
97 #define ATMEL_BASE_PIOA 0xfffff400
98 #define ATMEL_BASE_PIOB 0xfffff600
99 #define ATMEL_BASE_PIOC 0xfffff800
100 #define ATMEL_BASE_PIOD 0xfffffa00
101 #define ATMEL_BASE_PMC 0xfffffc00
102 #define ATMEL_BASE_RSTC 0xfffffe00
103 #define ATMEL_BASE_SHDWC 0xfffffe10
104 #define ATMEL_BASE_PIT 0xfffffe30
105 #define ATMEL_BASE_WDT 0xfffffe40
106 #define ATMEL_BASE_GPBR 0xfffffe60
107 #define ATMEL_BASE_RTC 0xfffffeb0
112 #define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
113 #define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
116 #define ATMEL_BASE_OHCI 0x00500000 /* USB Host controller */
118 #define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
119 #define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
120 #define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
121 #define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
127 #define ATMEL_BASE_CS0 0x10000000
128 #define ATMEL_BASE_CS1 0x20000000
129 #define ATMEL_BASE_CS2 0x30000000
130 #define ATMEL_BASE_CS3 0x40000000
131 #define ATMEL_BASE_CS4 0x50000000
132 #define ATMEL_BASE_CS5 0x60000000
135 #define ARCH_ID_AT91SAM9X5 0x819a05a0
136 #define ARCH_ID_VERSION_MASK 0x1f
137 #define ARCH_EXID_AT91SAM9G15 0x00000000
138 #define ARCH_EXID_AT91SAM9G35 0x00000001
139 #define ARCH_EXID_AT91SAM9X35 0x00000002
140 #define ARCH_EXID_AT91SAM9G25 0x00000003
141 #define ARCH_EXID_AT91SAM9X25 0x00000004
165 #define CONFIG_SYS_TIMER_COUNTER 0xfffffe3c
177 #define ATMEL_PMECC_INDEX_OFFSET_512 0x8000
178 #define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000