Lines Matching +full:24 +full:gbit
39 * V2 |2015.04.24 : 1.[P1] Add disabling all DRAM requests during PHY init
47 * V6 |2015.08.24 : 1.[P1] Fix SCU160 parameter value for CLKIN=25MHz condition
62 * V12|2016.06.24 : 1.[P1] Modify LPC Reset input source when eSPI mode enabled
95 * CONFIG_DDR3_8GSTACK // DDR3 8Gbit Stack die
96 * CONFIG_DDR4_4GX8 // DDR4 4Gbit X8 dual part
686 ldr r2, =0xC48066C0 @ load PLL parameter for 24Mhz CLKIN (330)
688 ldr r2, =0x93002400 @ load PLL parameter for 24Mhz CLKIN (396)
690 mov r1, r3, lsr #24 @ Check DDR4
694 ldr r2, =0x930023E0 @ load PLL parameter for 24Mhz CLKIN (384)
696 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (372)
698 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (360)
712 mov r1, r3, lsr #24 @ Check DDR4
716 ldr r2, =0x930023C0 @ load PLL parameter for 24Mhz CLKIN (387.5)
718 ldr r2, =0x930023A0 @ load PLL parameter for 24Mhz CLKIN (375)
720 ldr r2, =0x93002380 @ load PLL parameter for 24Mhz CLKIN (362.5)
725 ldr r0, =0x1e6e2160 @ set 24M Jitter divider (HPLL=825MHz)
957 ldr r2, =0x01000000 @ bit[24]=1 => DDR4
1365 orr r1, r1, r2, lsl #24
1370 orr r1, r1, r3, lsl #24
1830 cmp r2, r1 @ == 8Gbit
1832 moveq r7, r7, lsr #24
1838 cmp r2, r1 @ == 4Gbit
1846 cmp r2, r1 @ == 2Gbit