1 // SPDX-License-Identifier: GPL-2.0+
18 	writel(0, &pl310->pl310_cache_sync);  in pl310_cache_sync()
25 	assoc_16 = readl(&pl310->pl310_aux_ctrl) &  in pl310_background_op_all_ways()
32 	way_mask = (1 << associativity) - 1;  in pl310_background_op_all_ways()
43 	pl310_background_op_all_ways(&pl310->pl310_inv_way);  in v7_outer_cache_inval_all()
48 	pl310_background_op_all_ways(&pl310->pl310_clean_inv_way);  in v7_outer_cache_flush_all()
51 /* Flush(clean invalidate) memory from start to stop-1 */
52 void v7_outer_cache_flush_range(u32 start, u32 stop)  in v7_outer_cache_flush_range()  argument
58 	 * Align to the beginning of cache-line - this ensures that  in v7_outer_cache_flush_range()
61 	start &= ~(line_size - 1);  in v7_outer_cache_flush_range()
63 	for (pa = start; pa < stop; pa = pa + line_size)  in v7_outer_cache_flush_range()
64 		writel(pa, &pl310->pl310_clean_inv_line_pa);  in v7_outer_cache_flush_range()
69 /* invalidate memory from start to stop-1 */
70 void v7_outer_cache_inval_range(u32 start, u32 stop)  in v7_outer_cache_inval_range()  argument
76 	 * If start address is not aligned to cache-line do not  in v7_outer_cache_inval_range()
77 	 * invalidate the first cache-line  in v7_outer_cache_inval_range()
79 	if (start & (line_size - 1)) {  in v7_outer_cache_inval_range()
80 		printf("ERROR: %s - start address is not aligned - 0x%08x\n",  in v7_outer_cache_inval_range()
83 		start = (start + line_size - 1) & ~(line_size - 1);  in v7_outer_cache_inval_range()
87 	 * If stop address is not aligned to cache-line do not  in v7_outer_cache_inval_range()
88 	 * invalidate the last cache-line  in v7_outer_cache_inval_range()
90 	if (stop & (line_size - 1)) {  in v7_outer_cache_inval_range()
91 		printf("ERROR: %s - stop address is not aligned - 0x%08x\n",  in v7_outer_cache_inval_range()
92 			__func__, stop);  in v7_outer_cache_inval_range()
94 		stop &= ~(line_size - 1);  in v7_outer_cache_inval_range()
97 	for (pa = start; pa < stop; pa = pa + line_size)  in v7_outer_cache_inval_range()
98 		writel(pa, &pl310->pl310_inv_line_pa);  in v7_outer_cache_inval_range()