Lines Matching +full:0 +full:xc883c000
9 #define GX_FIRMWARE_MEM_SIZE 0x1000000
11 #define GX_AOBUS_BASE 0xc8100000
12 #define GX_PERIPHS_BASE 0xc8834400
13 #define GX_HIU_BASE 0xc883c000
14 #define GX_ETH_BASE 0xc9410000
19 #define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)
20 #define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)
21 #define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)
22 #define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95)
24 #define GX_AO_BOOT_DEVICE 0xF
25 #define GX_AO_MEM_SIZE_MASK 0xFFFF0000
27 #define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
29 #define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
34 /* GPIO registers 0 to 6 */
35 #define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
36 #define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
40 #define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50)
41 #define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51)
42 #define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56)
43 #define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57)
45 #define GX_ETH_REG_0_PHY_INTF BIT(0)
55 #define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)