Lines Matching +full:0 +full:x70000868
16 reg = <0x00003000 0x00000800 /* PADS registers */
17 0x00003800 0x00000200 /* AFI registers */
18 0x10000000 0x10000000>; /* configuration space */
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28 bus-range = <0x00 0xff>;
32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
36 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
37 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
50 pci@1,0 {
52 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
53 reg = <0x000800 0 0 0 0>;
63 pci@2,0 {
65 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
66 reg = <0x001000 0 0 0 0>;
76 pci@3,0 {
78 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
79 reg = <0x001800 0 0 0 0>;
92 reg = <0x50000000 0x00024000>;
102 ranges = <0x54000000 0x54000000 0x04000000>;
106 reg = <0x54040000 0x00040000>;
115 reg = <0x54080000 0x00040000>;
124 reg = <0x540c0000 0x00040000>;
133 reg = <0x54100000 0x00040000>;
142 reg = <0x54140000 0x00040000>;
151 reg = <0x54180000 0x00040000>;
162 reg = <0x54200000 0x00040000>;
172 nvidia,head = <0>;
181 reg = <0x54240000 0x00040000>;
200 reg = <0x54280000 0x00040000>;
212 reg = <0x542c0000 0x00040000>;
220 reg = <0x54300000 0x00040000>;
230 reg = <0x50040600 0x20>;
239 reg = <0x50041000 0x1000
240 0x50040100 0x0100>;
248 reg = <0x50043000 0x1000>;
257 reg = <0x60004000 0x100>,
258 <0x60004100 0x50>,
259 <0x60004200 0x50>,
260 <0x60004300 0x50>,
261 <0x60004400 0x50>;
269 reg = <0x60005000 0x400>;
270 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
281 reg = <0x60006000 0x1000>;
288 reg = <0x60007000 0x1000>;
293 reg = <0x6000a000 0x1400>;
334 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
339 reg = <0x6000d000 0x1000>;
353 gpio-ranges = <&pinmux 0 0 248>;
359 reg = <0x70000800 0x64 /* Chip revision */
360 0x70000008 0x04>; /* Strapping options */
365 reg = <0x70000868 0xd4 /* Pad control registers */
366 0x70003000 0x3e4>; /* Mux registers */
379 reg = <0x70006000 0x40>;
392 reg = <0x70006040 0x40>;
405 reg = <0x70006200 0x100>;
418 reg = <0x70006300 0x100>;
431 reg = <0x70006400 0x100>;
444 reg = <0x7000a000 0x100>;
454 reg = <0x7000e000 0x100>;
461 reg = <0x7000c000 0x100>;
464 #size-cells = <0>;
477 reg = <0x7000c400 0x100>;
480 #size-cells = <0>;
493 reg = <0x7000c500 0x100>;
496 #size-cells = <0>;
509 reg = <0x7000c700 0x100>;
512 #size-cells = <0>;
525 reg = <0x7000d000 0x100>;
528 #size-cells = <0>;
541 reg = <0x7000d400 0x200>;
544 #size-cells = <0>;
555 reg = <0x7000d600 0x200>;
558 #size-cells = <0>;
569 reg = <0x7000d800 0x200>;
572 #size-cells = <0>;
583 reg = <0x7000da00 0x200>;
586 #size-cells = <0>;
597 reg = <0x7000dc00 0x200>;
600 #size-cells = <0>;
611 reg = <0x7000de00 0x200>;
614 #size-cells = <0>;
625 reg = <0x7000e200 0x100>;
635 reg = <0x7000e400 0x400>;
642 reg = <0x7000f000 0x400>;
653 reg = <0x7000f800 0x400>;
662 reg = <0x70030000 0x10000>;
677 reg = <0x70080000 0x200
678 0x70080200 0x100>;
709 reg = <0x70080300 0x100>;
719 reg = <0x70080400 0x100>;
729 reg = <0x70080500 0x100>;
739 reg = <0x70080600 0x100>;
749 reg = <0x70080700 0x100>;
760 reg = <0x78000000 0x200>;
770 reg = <0x78000200 0x200>;
780 reg = <0x78000400 0x200>;
790 reg = <0x78000600 0x200>;
800 reg = <0x7d000000 0x4000>;
813 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
838 reg = <0x7d004000 0x4000>;
850 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
874 reg = <0x7d008000 0x4000>;
886 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
894 nvidia,hssync-start-delay = <0>;
910 #size-cells = <0>;
912 cpu@0 {
915 reg = <0>;