Lines Matching +full:spi0 +full:- +full:pins

1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3128-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
29 spi0 = &spi0;
42 arm-pmu {
43 compatible = "arm,cortex-a7-pmu";
51 #address-cells = <1>;
52 #size-cells = <0>;
53 enable-method = "rockchip,rk3128-smp";
57 compatible = "arm,cortex-a7";
59 operating-points = <
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
70 compatible = "arm,cortex-a7";
76 compatible = "arm,cortex-a7";
82 compatible = "arm,cortex-a7";
89 #address-cells = <1>;
90 #size-cells = <1>;
94 #address-cells = <1>;
95 #size-cells = <1>;
141 #address-cells = <1>;
142 #size-cells = <1>;
147 rockchip,read-latency = <0x3f>;
162 compatible = "arm,amba-bus";
163 #address-cells = <1>;
164 #size-cells = <1>;
165 interrupt-parent = <&gic>;
171 arm,pl330-broken-no-flushp;//2
174 #dma-cells = <1>;
176 clock-names = "apb_pclk";
181 compatible = "fixed-clock";
182 clock-frequency = <24000000>;
183 clock-output-names = "xin24m";
184 #clock-cells = <0>;
188 compatible = "fixed-clock";
190 clock-frequency = <12000000>;
191 clock-output-names = "xin12m";
192 #clock-cells = <0>;
196 compatible = "arm,armv7-timer";
197 arm,cpu-registers-not-fw-configured;
200 clock-frequency = <24000000>;
204 compatible = "arm,armv7-timer";
213 clock-names = "pclk_wdt";
224 #reset-cells = <1>;
228 compatible = "rockchip,rk-nandc";
231 pinctrl-names = "default";
232 pinctrl-0 = <&nandc_ale &nandc_cle &nandc_wrn &nandc_rdn &nandc_rdy &nandc_cs0 &nandc_data>;
237 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
241 u-boot,dm-pre-reloc;
242 compatible = "rockchip,rk3128-dmc", "syscon";
246 cru: clock-controller@20000000 {
247 u-boot,dm-pre-reloc;
248 compatible = "rockchip,rk3128-cru";
251 #clock-cells = <1>;
252 #reset-cells = <1>;
253 assigned-clocks = <&cru PLL_GPLL>;
254 assigned-clock-rates = <594000000>;
258 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
261 reg-shift = <2>;
262 reg-io-width = <4>;
263 clock-frequency = <24000000>;
265 clock-names = "baudclk", "apb_pclk";
266 pinctrl-names = "default";
267 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
269 #dma-cells = <2>;
273 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
276 reg-shift = <2>;
277 reg-io-width = <4>;
278 clock-frequency = <24000000>;
280 clock-names = "baudclk", "apb_pclk";
281 pinctrl-names = "default";
282 pinctrl-0 = <&uart1_xfer>;
284 #dma-cells = <2>;
288 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
291 reg-shift = <2>;
292 reg-io-width = <4>;
293 clock-frequency = <24000000>;
295 clock-names = "baudclk", "apb_pclk";
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart2_xfer>;
299 #dma-cells = <2>;
306 #io-channel-cells = <1>;
308 clock-names = "saradc", "apb_pclk";
310 reset-names = "saradc-apb";
315 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
317 #pwm-cells = <3>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pwm0_pin>;
321 clock-names = "pwm";
325 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
327 #pwm-cells = <3>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pwm1_pin>;
331 clock-names = "pwm";
335 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
337 #pwm-cells = <3>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&pwm2_pin>;
341 clock-names = "pwm";
345 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
347 #pwm-cells = <3>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pwm3_pin>;
351 clock-names = "pwm";
355 compatible = "rockchip,rk3128-smp-sram", "mmio-sram";
357 map-exec;
358 map-cacheable;
362 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
364 #address-cells = <1>;
365 #size-cells = <1>;
368 gic: interrupt-controller@10139000 {
369 compatible = "arm,gic-400";
370 interrupt-controller;
371 #interrupt-cells = <3>;
372 #address-cells = <0>;
380 u2phy: usb2-phy {
381 compatible = "rockchip,rk3128-usb2phy";
385 clock-names = "phyclk";
386 #clock-cells = <0>;
387 clock-output-names = "usb480m_phy";
388 #phy-cells = <1>;
391 u2phy_otg: otg-port {
392 #phy-cells = <0>;
396 interrupt-names = "otg-bvalid", "otg-id",
401 u2phy_host: host-port {
402 #phy-cells = <0>;
404 interrupt-names = "linestate";
410 compatible = "rockchip,rk3128-usb", "rockchip,rk3288-usb",
415 g-use-dma;
416 hnp-srp-disable;
418 phy-names = "usb";
423 compatible = "generic-ehci";
427 phy-names = "usb";
432 compatible = "generic-ohci";
436 phy-names = "usb";
441 compatible = "rockchip,rk312x-dw-mshc", "rockchip,rk3288-dw-mshc";
443 max-frequency = <150000000>;
447 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
448 fifo-depth = <0x100>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
451 bus-width = <4>;
456 u-boot,dm-pre-reloc;
457 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
459 max-frequency = <150000000>;
463 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
464 bus-width = <8>;
465 default-sample-phase = <158>;
466 num-slots = <1>;
467 fifo-depth = <0x100>;
468 pinctrl-names = "default";
469 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
471 reset-names = "reset";
476 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
479 #address-cells = <1>;
480 #size-cells = <0>;
481 clock-names = "i2c";
483 pinctrl-names = "default";
484 pinctrl-0 = <&i2c0_xfer>;
488 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 clock-names = "i2c";
495 pinctrl-names = "default";
496 pinctrl-0 = <&i2c1_xfer>;
500 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
503 #address-cells = <1>;
504 #size-cells = <0>;
505 clock-names = "i2c";
507 pinctrl-names = "default";
508 pinctrl-0 = <&i2c2_xfer>;
512 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
515 #address-cells = <1>;
516 #size-cells = <0>;
517 clock-names = "i2c";
519 pinctrl-names = "default";
520 pinctrl-0 = <&i2c3_xfer>;
523 spi0: spi@20074000 { label
524 compatible = "rockchip,rk3128-spi", "rockchip,rk3288-spi";
527 #address-cells = <1>;
528 #size-cells = <0>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&spi0_txd_mux0 &spi0_rxd_mux0 &spi0_clk_mux0 &spi0_cs0_mux0 &spi0_cs1_mux0>;
531 rockchip,spi-src-clk = <0>;
532 num-cs = <2>;
534 clock-names = "spi","pclk_spi0";
536 #dma-cells = <2>;
537 dma-names = "tx", "rx";
541 u-boot,dm-pre-reloc;
542 compatible = "rockchip,rk3128-grf", "syscon";
547 compatible = "rockchip,rk3128-pinctrl";
552 reg-names = "base", "mux", "pull", "drv";
554 #address-cells = <1>;
555 #size-cells = <1>;
559 compatible = "rockchip,gpio-bank";
563 gpio-controller;
564 #gpio-cells = <2>;
565 interrupt-controller;
566 #interrupt-cells = <2>;
570 compatible = "rockchip,gpio-bank";
574 gpio-controller;
575 #gpio-cells = <2>;
576 interrupt-controller;
577 #interrupt-cells = <2>;
581 compatible = "rockchip,gpio-bank";
585 gpio-controller;
586 #gpio-cells = <2>;
587 interrupt-controller;
588 #interrupt-cells = <2>;
592 compatible = "rockchip,gpio-bank";
596 gpio-controller;
597 #gpio-cells = <2>;
598 interrupt-controller;
599 #interrupt-cells = <2>;
602 pcfg_pull_up: pcfg-pull-up {
603 bias-pull-up;
606 pcfg_pull_down: pcfg-pull-down {
607 bias-pull-down;
610 pcfg_pull_none: pcfg-pull-none {
611 bias-disable;
620 emmc_clk: emmc-clk {
621 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
624 emmc_cmd: emmc-cmd {
625 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
628 emmc_pwren: emmc-pwren {
629 rockchip,pins = <2 5 RK_FUNC_2 &pcfg_pull_none>;
632 emmc_bus8: emmc-bus8 {
633 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
645 nandc_ale:nandc-ale {
646 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
649 nandc_cle:nandc-cle {
650 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
653 nandc_wrn:nandc-wrn {
654 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
657 nandc_rdn:nandc-rdn {
658 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
661 nandc_rdy:nandc-rdy {
662 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
665 nandc_cs0:nandc-cs0 {
666 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
669 nandc_data: nandc-data {
670 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
675 uart0_xfer: uart0-xfer {
676 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
680 uart0_cts: uart0-cts {
681 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
684 uart0_rts: uart0-rts {
685 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
690 uart1_xfer: uart1-xfer {
691 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
697 uart2_xfer: uart2-xfer {
698 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
704 sdmmc_clk: sdmmc-clk {
705 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
708 sdmmc_cmd: sdmmc-cmd {
709 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_up>;
712 sdmmc_wp: sdmmc-wp {
713 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up>;
716 sdmmc_pwren: sdmmc-pwren {
717 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up>;
720 sdmmc_bus4: sdmmc-bus4 {
721 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up>,
729 pwm0_pin: pwm0-pin {
730 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
735 pwm1_pin: pwm1-pin {
736 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
741 pwm2_pin: pwm2-pin {
742 rockchip,pins = <0 1 2 &pcfg_pull_none>;
747 pwm3_pin: pwm3-pin {
748 rockchip,pins = <0 27 1 &pcfg_pull_none>;
753 i2c0_xfer: i2c0-xfer {
754 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
760 i2c1_xfer: i2c1-xfer {
761 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
767 i2c2_xfer: i2c2-xfer {
768 rockchip,pins = <2 20 3 &pcfg_pull_none>,
774 i2c3_xfer: i2c3-xfer {
775 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
780 spi0 {
781 spi0_txd_mux0:spi0-txd-mux0 {
782 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
785 spi0_rxd_mux0:spi0-rxd-mux0 {
786 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
789 spi0_clk_mux0:spi0-clk-mux0 {
790 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
793 spi0_cs0_mux0:spi0-cs0-mux0 {
794 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
797 spi0_cs1_mux0:spi0-cs1-mux0 {
798 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;