arm/dts/meson-gxbb.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gx.dtsi"
7 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
8 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9 #include <dt-bindings/clock/gxbb-clkc.h>
10 #include <dt-bindings/clock/gxbb-aoclkc.h>
11 #include <dt-bindings/reset/gxbb-aoclkc.h>
14 	compatible = "amlogic,meson-gxbb";
18 			compatible = "amlogic,meson-gxbb-usb2-phy";
19 			#phy-cells = <0>;
22 			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23 			clock-names = "usb_general", "usb";
28 			compatible = "amlogic,meson-gxbb-usb2-phy";
29 			#phy-cells = <0>;
32 			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33 			clock-names = "usb_general", "usb";
38 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
41 			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42 			clock-names = "otg";
44 			phy-names = "usb2-phy";
50 			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
53 			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54 			clock-names = "otg";
56 			phy-names = "usb2-phy";
65 		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66 		#address-cells = <2>;
67 		#size-cells = <2>;
74 			reg-names = "mux", "pull", "gpio";
75 			gpio-controller;
76 			#gpio-cells = <2>;
77 			gpio-ranges = <&pinctrl_aobus 0 0 14>;
227 		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
239 		interrupt-names = "gp", "gpmmu", "pp", "pmu",
242 		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
243 		clock-names = "bus", "core";
250 		assigned-clocks = <&clkc CLKID_GP0_PLL>,
251 				  <&clkc CLKID_MALI_0_SEL>,
252 				  <&clkc CLKID_MALI_0>,
253 				  <&clkc CLKID_MALI>; /* Glitch free mux */
254 		assigned-clock-parents = <0>, /* Do Nothing */
255 					 <&clkc CLKID_GP0_PLL>,
257 					 <&clkc CLKID_MALI_0>;
258 		assigned-clock-rates = <744000000>,
267 		compatible = "amlogic,meson-gxbb-spifc";
269 		#address-cells = <1>;
270 		#size-cells = <0>;
271 		clocks = <&clkc CLKID_SPI>;
278 	clock-names = "core";
282 	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
286 	clocks = <&clkc CLKID_ETH>,
287 		 <&clkc CLKID_FCLK_DIV2>,
288 		 <&clkc CLKID_MPLL2>;
289 	clock-names = "stmmaceth", "clkin0", "clkin1";
293 	compatible = "amlogic,meson-gpio-intc",
294 		     "amlogic,meson-gxbb-gpio-intc";
299 	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
303 	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
304 	clocks = <&clkc CLKID_HDMI_PCLK>,
305 		 <&clkc CLKID_CLK81>,
306 		 <&clkc CLKID_GCLK_VENCI_INT0>;
307 	clock-names = "isfr", "iahb", "venci";
311 	clkc: clock-controller {  label
312 		compatible = "amlogic,gxbb-clkc";
313 		#clock-cells = <1>;
318 	clocks = <&clkc CLKID_RNG0>;
319 	clock-names = "core";
323 	clocks = <&clkc CLKID_I2C>;
327 	clocks = <&clkc CLKID_AO_I2C>;
331 	clocks = <&clkc CLKID_I2C>;
335 	clocks = <&clkc CLKID_I2C>;
340 		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
341 		#address-cells = <2>;
342 		#size-cells = <2>;
350 			reg-names = "mux", "pull", "pull-enable", "gpio";
351 			gpio-controller;
352 			#gpio-cells = <2>;
353 			gpio-ranges = <&pinctrl_periphs 0 0 119>;
365 		emmc_ds_pins: emmc-ds {
377 			cfg-pull-down {
379 				bias-pull-down;
393 		spi_pins: spi-pins {
402 		spi_ss0_pins: spi-ss0 {
426 			cfg-pull-down {
428 				bias-pull-down;
449 			cfg-pull-down {
451 				bias-pull-down;
534 		eth_rgmii_pins: eth-rgmii {
554 		eth_rmii_pins: eth-rmii {
675 	clocks = <&clkc CLKID_VPU>,
676 	         <&clkc CLKID_VAPB>;
677 	clock-names = "vpu", "vapb";
684 	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
685 			  <&clkc CLKID_VPU_0>,
686 			  <&clkc CLKID_VPU>, /* Glitch free mux */
687 			  <&clkc CLKID_VAPB_0_SEL>,
688 			  <&clkc CLKID_VAPB_0>,
689 			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
690 	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
692 				 <&clkc CLKID_VPU_0>,
693 				 <&clkc CLKID_FCLK_DIV4>,
695 				 <&clkc CLKID_VAPB_0>;
696 	assigned-clock-rates = <0>, /* Do Nothing */
705 	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
707 		 <&clkc CLKID_SAR_ADC>,
708 		 <&clkc CLKID_SAR_ADC_CLK>,
709 		 <&clkc CLKID_SAR_ADC_SEL>;
710 	clock-names = "clkin", "core", "adc_clk", "adc_sel";
714 	clocks = <&clkc CLKID_SD_EMMC_A>,
715 		 <&clkc CLKID_SD_EMMC_A_CLK0>,
716 		 <&clkc CLKID_FCLK_DIV2>;
717 	clock-names = "core", "clkin0", "clkin1";
722 	clocks = <&clkc CLKID_SD_EMMC_B>,
723 		 <&clkc CLKID_SD_EMMC_B_CLK0>,
724 		 <&clkc CLKID_FCLK_DIV2>;
725 	clock-names = "core", "clkin0", "clkin1";
730 	clocks = <&clkc CLKID_SD_EMMC_C>,
731 		 <&clkc CLKID_SD_EMMC_C_CLK0>,
732 		 <&clkc CLKID_FCLK_DIV2>;
733 	clock-names = "core", "clkin0", "clkin1";
738 	clocks = <&clkc CLKID_SPICC>;
739 	clock-names = "core";
741 	num-cs = <1>;
745 	clocks = <&clkc CLKID_SPI>;
749 	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
750 	clock-names = "xtal", "pclk", "baud";
755 	clock-names = "xtal", "pclk", "baud";
760 	clock-names = "xtal", "pclk", "baud";
764 	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
765 	clock-names = "xtal", "pclk", "baud";
769 	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
770 	clock-names = "xtal", "pclk", "baud";
774 	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
775 	power-domains = <&pwrc_vpu>;