Lines Matching +full:anatop +full:- +full:reg +full:- +full:offset
9 #include <dt-bindings/clock/imx6sll-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx6sll-pinfunc.h"
43 #address-cells = <1>;
44 #size-cells = <0>;
47 compatible = "arm,cortex-a9";
49 reg = <0>;
50 next-level-cache = <&L2>;
51 operating-points = <
58 fsl,soc-operating-points = <
59 /* ARM kHz SOC-PU uV */
65 clock-latency = <61036>; /* two CLK32 periods */
66 fsl,low-power-run;
75 clock-names = "arm", "pll2_pfd2_396m", "step",
81 intc: interrupt-controller@00a01000 {
82 compatible = "arm,cortex-a9-gic";
83 #interrupt-cells = <3>;
84 interrupt-controller;
85 reg = <0x00a01000 0x1000>,
87 interrupt-parent = <&intc>;
91 #address-cells = <1>;
92 #size-cells = <0>;
95 compatible = "fixed-clock";
96 reg = <0>;
97 #clock-cells = <0>;
98 clock-frequency = <32768>;
99 clock-output-names = "ckil";
103 compatible = "fixed-clock";
104 reg = <1>;
105 #clock-cells = <0>;
106 clock-frequency = <24000000>;
107 clock-output-names = "osc";
111 compatible = "fixed-clock";
112 reg = <2>;
113 #clock-cells = <0>;
114 clock-frequency = <0>;
115 clock-output-names = "ipp_di0";
119 compatible = "fixed-clock";
120 reg = <3>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
123 clock-output-names = "ipp_di1";
128 #address-cells = <1>;
129 #size-cells = <1>;
130 compatible = "simple-bus";
131 interrupt-parent = <&gpc>;
147 clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
155 compatible = "fsl,lpm-sram";
156 reg = <0x00900000 0x4000>;
160 compatible = "fsl,ddr-lpm-sram";
161 reg = <0x00904000 0x1000>;
165 compatible = "mmio-sram";
166 reg = <0x00905000 0x1B000>;
169 L2: l2-cache@00a02000 {
170 compatible = "arm,pl310-cache";
171 reg = <0x00a02000 0x1000>;
173 cache-unified;
174 cache-level = <2>;
175 arm,tag-latency = <4 2 3>;
176 arm,data-latency = <4 2 3>;
179 aips1: aips-bus@02000000 {
180 compatible = "fsl,aips-bus", "simple-bus";
181 #address-cells = <1>;
182 #size-cells = <1>;
183 reg = <0x02000000 0x100000>;
186 spba: spba-bus@02000000 {
187 compatible = "fsl,spba-bus", "simple-bus";
188 #address-cells = <1>;
189 #size-cells = <1>;
190 reg = <0x02000000 0x40000>;
194 compatible = "fsl,imx6sl-spdif", "fsl,imx35-spdif";
195 reg = <0x02004000 0x4000>;
198 dma-names = "rx", "tx";
209 clock-names = "core", "rxtx0",
218 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
219 reg = <0x02008000 0x4000>;
222 dma-names = "rx", "tx";
225 clock-names = "ipg", "per";
230 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
231 reg = <0x0200c000 0x4000>;
234 dma-names = "rx", "tx";
237 clock-names = "ipg", "per";
242 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
243 reg = <0x02010000 0x4000>;
246 dma-names = "rx", "tx";
249 clock-names = "ipg", "per";
254 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02014000 0x4000>;
258 dma-names = "rx", "tx";
261 clock-names = "ipg", "per";
266 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
267 reg = <0x02018000 0x4000>;
270 dma-names = "rx", "tx";
273 clock-names = "ipg", "per";
278 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
279 reg = <0x02020000 0x4000>;
282 dma-names = "rx", "tx";
285 clock-names = "ipg", "per";
290 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
291 reg = <0x02024000 0x4000>;
294 dma-names = "rx", "tx";
297 clock-names = "ipg", "per";
302 compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
303 reg = <0x02028000 0x4000>;
306 dma-names = "rx", "tx";
307 fsl,fifo-depth = <15>;
310 clock-names = "ipg", "baud";
315 compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
316 reg = <0x0202c000 0x4000>;
319 dma-names = "rx", "tx";
320 fsl,fifo-depth = <15>;
323 clock-names = "ipg", "baud";
328 compatible = "fsl,imx6sll-ssi", "fsl,imx51-ssi";
329 reg = <0x02030000 0x4000>;
332 dma-names = "rx", "tx";
333 fsl,fifo-depth = <15>;
336 clock-names = "ipg", "baud";
341 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
342 reg = <0x02034000 0x4000>;
345 dma-name = "rx", "tx";
348 clock-names = "ipg", "per";
354 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
355 reg = <0x02080000 0x4000>;
359 clock-names = "ipg", "per";
360 #pwm-cells = <2>;
364 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
365 reg = <0x02084000 0x4000>;
369 clock-names = "ipg", "per";
370 #pwm-cells = <2>;
374 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
375 reg = <0x02088000 0x4000>;
379 clock-names = "ipg", "per";
380 #pwm-cells = <2>;
384 compatible = "fsl,imx6sll-pwm", "fsl,imx27-pwm";
385 reg = <0x0208c000 0x4000>;
389 clock-names = "ipg", "per";
390 #pwm-cells = <2>;
394 compatible = "fsl,imx6sll-gpt";
395 reg = <0x02098000 0x4000>;
399 clock-names = "ipg", "per";
403 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
404 reg = <0x0209c000 0x4000>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
414 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
415 reg = <0x020a0000 0x4000>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
425 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
426 reg = <0x020a4000 0x4000>;
429 gpio-controller;
430 #gpio-cells = <2>;
431 interrupt-controller;
432 #interrupt-cells = <2>;
436 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
437 reg = <0x020a8000 0x4000>;
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
447 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
448 reg = <0x020ac000 0x4000>;
451 gpio-controller;
452 #gpio-cells = <2>;
453 interrupt-controller;
454 #interrupt-cells = <2>;
458 compatible = "fsl,imx6sll-gpio", "fsl,imx35-gpio";
459 reg = <0x020b0000 0x4000>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
469 compatible = "fsl,imx6sll-kpp", "fsl,imx21-kpp";
470 reg = <0x020b8000 0x4000>;
477 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
478 reg = <0x020bc000 0x4000>;
484 compatible = "fsl,imx6sll-wdt", "fsl,imx21-wdt";
485 reg = <0x020c0000 0x4000>;
492 compatible = "fsl,imx6sll-ccm";
493 reg = <0x020c4000 0x4000>;
496 #clock-cells = <1>;
498 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
501 anatop: anatop@020c8000 { label
502 compatible = "fsl,imx6sll-anatop",
503 "fsl,imx6q-anatop",
504 "syscon", "simple-bus";
505 reg = <0x020c8000 0x4000>;
510 reg_3p0: regulator-3p0@120 {
511 compatible = "fsl,anatop-regulator";
512 regulator-name = "vdd3p0";
513 regulator-min-microvolt = <2625000>;
514 regulator-max-microvolt = <3400000>;
515 anatop-reg-offset = <0x120>;
516 anatop-vol-bit-shift = <8>;
517 anatop-vol-bit-width = <5>;
518 anatop-min-bit-val = <0>;
519 anatop-min-voltage = <2625000>;
520 anatop-max-voltage = <3400000>;
521 anatop-enable-bit = <0>;
526 compatible = "fsl,imx6sll-tempmon", "fsl,imx6sx-tempmon";
528 fsl,tempmon = <&anatop>;
529 fsl,tempmon-data = <&ocotp>;
535 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
536 "fsl,imx23-usbphy";
537 reg = <0x020c9000 0x1000>;
540 phy-3p0-supply = <®_3p0>;
541 fsl,anatop = <&anatop>;
545 compatible = "fsl,imx6sll-usbphy", "fsl,imx6ul-usbphy",
546 "fsl,imx23-usbphy";
547 reg = <0x020ca000 0x1000>;
550 phy-reg_3p0-supply = <®_3p0>;
551 fsl,anatop = <&anatop>;
555 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
556 reg = <0x020cc000 0x4000>;
558 snvs_rtc: snvs-rtc-lp {
559 compatible = "fsl,sec-v4.0-mon-rtc-lp";
561 offset = <0x34>;
565 snvs_poweroff: snvs-poweroff {
566 compatible = "syscon-poweroff";
568 offset = <0x38>;
572 snvs_pwrkey: snvs-powerkey {
573 compatible = "fsl,sec-v4.0-pwrkey";
582 reg = <0x020d0000 0x4000>;
587 reg = <0x020d4000 0x4000>;
592 compatible = "fsl,imx6sll-src", "fsl,imx51-src";
593 reg = <0x020d8000 0x4000>;
596 #reset-cells = <1>;
600 compatible = "fsl,imx6sll-gpc", "fsl,imx6q-gpc";
601 reg = <0x020dc000 0x4000>;
602 interrupt-controller;
603 #interrupt-cells = <3>;
605 interrupt-parent = <&intc>;
606 fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
610 compatible = "fsl,imx6sll-iomuxc";
611 reg = <0x020e0000 0x4000>;
614 gpr: iomuxc-gpr@020e4000 {
615 compatible = "fsl,imx6sll-iomuxc-gpr",
616 "fsl,imx6q-iomuxc-gpr", "syscon";
617 reg = <0x020e4000 0x4000>;
621 compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
622 reg = <0x020e8000 0x4000>;
627 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
632 compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma";
633 reg = <0x020ec000 0x4000>;
637 clock-names = "ipg", "ahb";
638 #dma-cells = <3>;
640 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
644 compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma";
645 reg = <0x020f0000 0x4000>;
650 clock-names = "pxp_ipg", "pxp_axi";
655 compatible = "fsl,imx6sll-epdc", "fsl,imx7d-epdc";
656 reg = <0x020f4000 0x4000>;
659 clock-names = "epdc_axi", "epdc_pix";
664 compatible = "fsl,imx6sll-lcdif", "fsl,imx28-lcdif";
665 reg = <0x020f8000 0x4000>;
670 clock-names = "pix", "axi", "disp_axi";
675 compatible = "fsl,imx6sl-dcp";
676 reg = <0x020fc000 0x4000>;
681 clock-names = "dcp";
685 aips2: aips-bus@02100000 {
686 compatible = "fsl,aips-bus", "simple-bus";
687 #address-cells = <1>;
688 #size-cells = <1>;
689 reg = <0x02100000 0x100000>;
693 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
694 "fsl,imx27-usb";
695 reg = <0x02184000 0x200>;
700 fsl,anatop = <&anatop>;
701 ahb-burst-config = <0x0>;
702 tx-burst-size-dword = <0x10>;
703 rx-burst-size-dword = <0x10>;
708 compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb",
709 "fsl,imx27-usb";
710 reg = <0x02184200 0x200>;
715 ahb-burst-config = <0x0>;
716 tx-burst-size-dword = <0x10>;
717 rx-burst-size-dword = <0x10>;
722 #index-cells = <1>;
723 compatible = "fsl,imx6sll-usbmisc", "fsl,imx6ul-usbmisc",
724 "fsl,imx6q-usbmisc";
725 reg = <0x02184800 0x200>;
729 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
730 reg = <0x02190000 0x4000>;
735 clock-names = "ipg", "ahb", "per";
736 bus-width = <4>;
737 fsl,tuning-step = <2>;
738 fsl,tuning-start-tap = <20>;
743 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
744 reg = <0x02194000 0x4000>;
749 clock-names = "ipg", "ahb", "per";
750 bus-width = <4>;
751 fsl,tuning-step = <2>;
752 fsl,tuning-start-tap = <20>;
757 compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc";
758 reg = <0x02198000 0x4000>;
763 clock-names = "ipg", "ahb", "per";
764 bus-width = <4>;
765 fsl,tuning-step = <2>;
766 fsl,tuning-start-tap = <20>;
771 #address-cells = <1>;
772 #size-cells = <0>;
773 compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
774 reg = <0x021a0000 0x4000>;
781 #address-cells = <1>;
782 #size-cells = <0>;
783 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
784 reg = <0x021a4000 0x4000>;
791 #address-cells = <1>;
792 #size-cells = <0>;
793 compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
794 reg = <0x021a8000 0x4000>;
801 compatible = "fsl,imx6sll-romcp", "syscon";
802 reg = <0x021ac000 0x4000>;
806 compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";
807 reg = <0x021b0000 0x4000>;
811 compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng";
812 reg = <0x021b4000 0x4000>;
817 ocotp: ocotp-ctrl@021bc000 {
818 compatible = "fsl,imx6sll-ocotp", "syscon";
819 reg = <0x021bc000 0x4000>;
824 compatible = "fsl,imx6sll-csu";
825 reg = <0x021c0000 0x4000>;
830 snvs_gpr: snvs-gpr@0x021c4000 {
831 compatible = "fsl, imx6sll-snvs-gpr";
832 reg = <0x021c4000 0x10000>;
835 iomuxc_snvs: iomuxc-snvs@021c8000 {
836 compatible = "fsl,imx6sll-iomuxc-snvs";
837 reg = <0x021c80000 0x10000>;
841 compatible = "fsl,imx6sll-audmux", "fsl,imx31-audmux";
842 reg = <0x021d8000 0x4000>;
847 compatible = "fsl,imx6sll-uart", "fsl,imx6q-uart", "fsl,imx21-uart";
848 reg = <0x021f4000 0x4000>;
851 dma-names = "rx", "tx";
854 clock-names = "ipg", "per";