Lines Matching +full:non +full:- +full:active

1 // SPDX-License-Identifier: GPL-2.0+ OR X11
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
17 /* DRAM space - 1, size : 2 GB DRAM */
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
24 #interrupt-cells = <3>;
25 interrupt-controller;
30 compatible = "arm,armv8-timer";
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
41 clock-frequency = <0>; /* Updated by bootloader */
49 clock-frequency = <0>; /* Updated by bootloader */
53 fsl_mc: fsl-mc@80c000000 {
54 compatible = "fsl,qoriq-mc";
60 compatible = "fsl,vf610-dspi";
61 #address-cells = <1>;
62 #size-cells = <0>;
65 num-cs = <6>;
69 compatible = "fsl,vf610-qspi";
70 #address-cells = <1>;
71 #size-cells = <0>;
74 reg-names = "QuadSPI", "QuadSPI-memory";
75 num-cs = <4>;
82 little-endian;
83 bus-width = <4>;
87 compatible = "fsl,layerscape-dwc3";
94 compatible = "fsl,layerscape-dwc3";
101 compatible = "fsl,ls-pcie", "snps,dw-pcie";
105 reg-names = "dbi", "lut", "config";
106 #address-cells = <3>;
107 #size-cells = <2>;
109 num-lanes = <4>;
110 bus-range = <0x0 0xff>;
112 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
116 compatible = "fsl,ls-pcie", "snps,dw-pcie";
120 reg-names = "dbi", "lut", "config";
121 #address-cells = <3>;
122 #size-cells = <2>;
124 num-lanes = <4>;
125 bus-range = <0x0 0xff>;
127 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
131 compatible = "fsl,ls-pcie", "snps,dw-pcie";
135 reg-names = "dbi", "lut", "config";
136 #address-cells = <3>;
137 #size-cells = <2>;
139 num-lanes = <8>;
140 bus-range = <0x0 0xff>;
142 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
146 compatible = "fsl,ls-pcie", "snps,dw-pcie";
150 reg-names = "dbi", "lut", "config";
151 #address-cells = <3>;
152 #size-cells = <2>;
154 num-lanes = <4>;
155 bus-range = <0x0 0xff>;
157 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
161 compatible = "fsl,ls2080a-ahci";