Lines Matching +full:fsl +full:- +full:i2c
1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright (C) 2014-2015, Freescale Semiconductor
13 compatible = "fsl,ls1043a";
14 interrupt-parent = <&gic>;
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
25 #interrupt-cells = <3>;
26 interrupt-controller;
35 compatible = "simple-bus";
36 #address-cells = <2>;
37 #size-cells = <2>;
41 compatible = "fsl,ls1043a-clockgen";
43 #clock-cells = <2>;
48 compatible = "fsl,vf610-dspi";
49 #address-cells = <1>;
50 #size-cells = <0>;
53 clock-names = "dspi";
55 num-cs = <6>;
56 big-endian;
61 compatible = "fsl,vf610-dspi";
62 #address-cells = <1>;
63 #size-cells = <0>;
66 clock-names = "dspi";
68 num-cs = <6>;
69 big-endian;
74 compatible = "fsl,esdhc";
77 big-endian;
78 bus-width = <4>;
82 compatible = "fsl,ifc", "simple-bus";
87 i2c0: i2c@2180000 {
88 compatible = "fsl,vf610-i2c";
89 #address-cells = <1>;
90 #size-cells = <0>;
93 clock-names = "i2c";
98 i2c1: i2c@2190000 {
99 compatible = "fsl,vf610-i2c";
100 #address-cells = <1>;
101 #size-cells = <0>;
104 clock-names = "i2c";
109 i2c2: i2c@21a0000 {
110 compatible = "fsl,vf610-i2c";
111 #address-cells = <1>;
112 #size-cells = <0>;
115 clock-names = "i2c";
120 i2c3: i2c@21b0000 {
121 compatible = "fsl,vf610-i2c";
122 #address-cells = <1>;
123 #size-cells = <0>;
126 clock-names = "i2c";
132 compatible = "fsl,ns16550", "ns16550a";
139 compatible = "fsl,ns16550", "ns16550a";
146 compatible = "fsl,ns16550", "ns16550a";
153 compatible = "fsl,ns16550", "ns16550a";
160 compatible = "fsl,ls1021a-lpuart";
164 clock-names = "ipg";
169 compatible = "fsl,ls1021a-lpuart";
173 clock-names = "ipg";
178 compatible = "fsl,ls1021a-lpuart";
181 clock-names = "ipg";
187 compatible = "fsl,ls1021a-lpuart";
191 clock-names = "ipg";
196 compatible = "fsl,ls1021a-lpuart";
200 clock-names = "ipg";
205 compatible = "fsl,ls1021a-lpuart";
209 clock-names = "ipg";
213 compatible = "fsl,vf610-qspi";
214 #address-cells = <1>;
215 #size-cells = <0>;
218 reg-names = "QuadSPI", "QuadSPI-memory";
219 num-cs = <2>;
220 big-endian;
225 compatible = "fsl,layerscape-dwc3";
232 compatible = "fsl,layerscape-dwc3";
239 compatible = "fsl,layerscape-dwc3";
246 compatible = "fsl,ls-pcie", "snps,dw-pcie";
250 reg-names = "dbi", "lut", "config";
251 big-endian;
252 #address-cells = <3>;
253 #size-cells = <2>;
255 bus-range = <0x0 0xff>;
257 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
261 compatible = "fsl,ls-pcie", "snps,dw-pcie";
265 reg-names = "dbi", "lut", "config";
266 big-endian;
267 #address-cells = <3>;
268 #size-cells = <2>;
270 num-lanes = <2>;
271 bus-range = <0x0 0xff>;
273 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
277 compatible = "fsl,ls-pcie", "snps,dw-pcie";
281 reg-names = "dbi", "lut", "config";
282 big-endian;
283 #address-cells = <3>;
284 #size-cells = <2>;
286 bus-range = <0x0 0xff>;
288 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
292 compatible = "fsl,ls1043a-ahci";