arm/dts/fsl-ls1012a.dtsi

1 // SPDX-License-Identifier: GPL-2.0+ OR X11
9 	compatible = "fsl,ls1012a";
10 	interrupt-parent = <&gic>;
13 		compatible = "fixed-clock";
14 		#clock-cells = <0>;
15 		clock-frequency = <100000000>;
16 		clock-output-names = "sysclk";
19 	gic: interrupt-controller@1400000 {
20 		compatible = "arm,gic-400";
21 		#interrupt-cells = <3>;
22 		interrupt-controller;
31 		compatible = "simple-bus";
32 		#address-cells = <2>;
33 		#size-cells = <2>;
37 			compatible = "fsl,ls1012a-clockgen";
39 			#clock-cells = <2>;
44 			compatible = "fsl,vf610-dspi";
45 			#address-cells = <1>;
46 			#size-cells = <0>;
49 			clock-names = "dspi";
51 			num-cs = <6>;
52 			big-endian;
57 			compatible = "fsl,esdhc";
60 			big-endian;
61 			bus-width = <4>;
65 			compatible = "fsl,esdhc";
68 			big-endian;
69 			non-removable;
70 			bus-width = <4>;
73 		i2c0: i2c@2180000 {
74 			compatible = "fsl,vf610-i2c";
75 			#address-cells = <1>;
76 			#size-cells = <0>;
79 			clock-names = "i2c";
84 		i2c1: i2c@2190000 {
85 			compatible = "fsl,vf610-i2c";
86 			#address-cells = <1>;
87 			#size-cells = <0>;
90 			clock-names = "i2c";
96 			compatible = "fsl,ns16550", "ns16550a";
103 			compatible = "fsl,ns16550", "ns16550a";
110 			compatible = "fsl,vf610-qspi";
111 			#address-cells = <1>;
112 			#size-cells = <0>;
115 			reg-names = "QuadSPI", "QuadSPI-memory";
116 			num-cs = <1>;
117 			big-endian;
122 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
127 			reg-names = "dbi", "lut", "ctrl", "config";
128 			big-endian;
129 			#address-cells = <3>;
130 			#size-cells = <2>;
132 			bus-range = <0x0 0xff>;
134 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
138 			compatible = "fsl,ls1012a-ahci";
146 			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
150 			fsl,usb-erratum-a005697;
154 			compatible = "fsl,layerscape-dwc3";