arm/dts/fsl-imx8mq.dtsi

16 #include "fsl-imx8-ca53.dtsi"
17 #include <dt-bindings/clock/imx8mq-clock.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/input/input.h>
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
21 #include <dt-bindings/pinctrl/pins-imx8mq.h>
22 #include <dt-bindings/thermal/thermal.h>
26 	interrupt-parent = <&gpc>;
27 	#address-cells = <2>;
28 	#size-cells = <2>;
50 	gic: interrupt-controller@38800000 {
51 		compatible = "arm,gic-v3";
54 		#interrupt-cells = <3>;
55 		interrupt-controller;
57 		interrupt-parent = <&gic>;
61 		compatible = "arm,armv8-timer";
65 			     IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
70 		clock-frequency = <8333333>;
71 		interrupt-parent = <&gic>;
74 	power: power-controller {
75 		compatible = "fsl,imx8mq-pm-domain";
76 		num-domains = <11>;
77 		#power-domain-cells = <1>;
81 		compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
84 		clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
85 			 <&clk IMX8MQ_CLK_PWM2_ROOT>;
86 		clock-names = "ipg", "per";
87 		#pwm-cells = <2>;
92 		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
96 		gpio-controller;
97 		#gpio-cells = <2>;
98 		interrupt-controller;
99 		#interrupt-cells = <2>;
103 		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
107 		gpio-controller;
108 		#gpio-cells = <2>;
109 		interrupt-controller;
110 		#interrupt-cells = <2>;
114 		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
118 		gpio-controller;
119 		#gpio-cells = <2>;
120 		interrupt-controller;
121 		#interrupt-cells = <2>;
125 		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
129 		gpio-controller;
130 		#gpio-cells = <2>;
131 		interrupt-controller;
132 		#interrupt-cells = <2>;
136 		compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
140 		gpio-controller;
141 		#gpio-cells = <2>;
142 		interrupt-controller;
143 		#interrupt-cells = <2>;
147 		compatible = "fsl,imx8mq-tmu";
150 		little-endian;
151 		u-boot,dm-pre-reloc;
152 		fsl,tmu-range = <0xa0000 0x90026 0x8004a 0x1006a>;
153 		fsl,tmu-calibration = <0x00000000 0x00000020
196 		#thermal-sensor-cells =  <0>;
199 	thermal-zones {
201 		cpu-thermal {
202 			polling-delay-passive = <250>;
203 			polling-delay = <2000>;
204 			thermal-sensors = <&tmu>;
218 			cooling-maps {
221 					cooling-device =
229 		compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
231 		clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_DIV>,
232 			 <&clk IMX8MQ_CLK_DUMMY>,
233 			 <&clk IMX8MQ_CLK_DUMMY>;
234 		clock-names = "pix", "axi", "disp_axi";
235 		assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>;
236 		assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
237 		assigned-clock-rate = <594000000>;
243 		compatible = "fsl,imx8mq-iomuxc";
247 	gpr: iomuxc-gpr@30340000 {
248 		compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx7d-iomuxc-gpr", "syscon";
252 	ocotp: ocotp-ctrl@30350000 {
253 		compatible = "fsl,imx8mq-ocotp", "fsl,imx7d-ocotp", "syscon";
258 		compatible = "fsl,imx8mq-anatop", "fsl,imx6q-anatop",
259 			"syscon", "simple-bus";
264 	clk: ccm@30380000 {  label
265 		compatible = "fsl,imx8mq-ccm";
269 		#clock-cells = <1>;
273 		compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc", "syscon";
275 		interrupt-controller;
277 		#interrupt-cells = <3>;
278 		interrupt-parent = <&gic>;
282 		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
285 		clocks = <&clk IMX8MQ_CLK_DUMMY>,
286 			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
287 			<&clk IMX8MQ_CLK_USDHC1_ROOT>;
288 		clock-names = "ipg", "ahb", "per";
289 		assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_DIV>;
290 		assigned-clock-rates = <400000000>;
291 		fsl,tuning-start-tap = <20>;
292 		fsl,tuning-step= <2>;
293 		bus-width = <4>;
298 		compatible = "fsl,imx8mq-usdhc", "fsl,imx7d-usdhc";
301 		clocks = <&clk IMX8MQ_CLK_DUMMY>,
302 			<&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
303 			<&clk IMX8MQ_CLK_USDHC2_ROOT>;
304 		clock-names = "ipg", "ahb", "per";
305 		fsl,tuning-start-tap = <20>;
306 		fsl,tuning-step= <2>;
307 		bus-width = <4>;
312 		compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
317 		clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
318 			<&clk IMX8MQ_CLK_ENET1_ROOT>,
319 			<&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
320 			<&clk IMX8MQ_CLK_ENET_REF_DIV>,
321 			<&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
322 		clock-names = "ipg", "ahb", "ptp",
324 		assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
325 				  <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
326 				  <&clk IMX8MQ_CLK_ENET_REF_SRC>,
327 				  <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
328 		assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
329 					 <&clk IMX8MQ_SYS2_PLL_100M>,
330 					 <&clk IMX8MQ_SYS2_PLL_125M>;
331 		assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
332 		stop-mode = <&gpr 0x10 3>;
333 		fsl,num-tx-queues=<3>;
334 		fsl,num-rx-queues=<3>;
340 		compatible = "fsl,mxc-ion";
341 		fsl,heap-id = <0>;
345 		#address-cells = <1>;
346 		#size-cells = <0>;
347 		compatible = "fsl,imx21-i2c";
350 		clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
355 		#address-cells = <1>;
356 		#size-cells = <0>;
357 		compatible = "fsl,imx21-i2c";
360 		clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
365 		#address-cells = <1>;
366 		#size-cells = <0>;
367 		compatible = "fsl,imx21-i2c";
370 		clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
375 		#address-cells = <1>;
376 		#size-cells = <0>;
377 		compatible = "fsl,imx21-i2c";
380 		clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
385 			compatible = "fsl,imx21-wdt";
388 			clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
393 			compatible = "fsl,imx21-wdt";
396 			clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
401 			compatible = "fsl,imx21-wdt";
404 			clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
409 		compatible = "dma-capability";
410 		only-dma-mask32 = <1>;
414 		#address-cells = <1>;
415 		#size-cells = <0>;
416 		compatible = "fsl,imx7d-qspi";
418 		reg-names = "QuadSPI", "QuadSPI-memory";
420 		clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
421 		<&clk IMX8MQ_CLK_QSPI_ROOT>;
422 		clock-names = "qspi_en", "qspi";
428 	#cooling-cells = <2>;