Lines Matching refs:x1
33 ldr x1, =GICC_BASE
52 ldr x1, =GICC_BASE_64K
83 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
91 ldr x1, =0x00000010
107 ldr x1, =0x00000020
110 ldr x1, =0x00000020
117 ldr x1, =CCI_MN_RNF_NODEID_LIST
123 ldr x1, =0x00FF000C
126 ldr x1, =0x00FF000C
129 ldr x1, =0x00FF000C
133 ldr x1, =0x00FF000C
136 ldr x1, =0x00FF000C
139 ldr x1, =0x00FF000C
143 ldr x1, =0x00FF000C
146 ldr x1, =0x00FF000C
149 ldr x1, =0x00FF000C
153 ldr x1, =0x00FF000C
156 ldr x1, =0x00FF000C
159 ldr x1, =0x00FF000C
163 ldr x1, =0x00FF000C
166 ldr x1, =0x00FF000C
169 ldr x1, =0x00FF000C
173 ldr x1, =0x00FF000C
176 ldr x1, =0x00FF000C
179 ldr x1, =0x00FF000C
185 ldr x1, =SMMU_BASE
186 ldr w0, [x1, #0x10]
188 str w0, [x1, #0x10]
207 branch_if_master x0, x1, 2f
215 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
219 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
221 str w0, [x1]
252 mov x1, #0x8
253 add x1, x1, x14
255 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
257 str w0, [x1]
259 mov x1, #0x110
260 add x1, x1, x14
262 ldr w0, [x1] /* Region-0 Attributes Register */
265 str w0, [x1]
267 mov x1, #0x114
268 add x1, x1, x14
270 ldr w0, [x1] /* Region-0 Access Register */
272 str w0, [x1]
291 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
294 mrs x1, S3_1_c11_c0_2
297 bic x1, x1, x0
299 orr x1, x1, #0x2
301 orr x1, x1, #0x80
302 msr S3_1_c11_c0_2, x1
328 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
333 cmp x0, x1
352 ldr x1, =FSL_LSCH3_SVR
353 ldr w0, [x1]
362 mov x1, x0
371 cmp x2, x1 /* check status */
388 mov x1, x0
396 orr x2, x2, x1
471 ubfm x1, x0, #8, #15
473 orr x10, x2, x1, lsl #2 /* x10 has LPID */
479 lsl x1, x10, #6
482 add x11, x1, x0
495 mov x0, x1
504 mrs x1, sctlr_el2
506 mrs x1, sctlr_el1
508 tbz x1, #25, cpu_is_le
542 ubfm x1, x0, #8, #15
544 orr x10, x2, x1, lsl #2 /* x10 has LPID */
546 lsl x1, x10, #6
549 add x11, x1, x0