Lines Matching +full:pulse +full:- +full:code

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
20 	setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);  in reset_cpu()
22 	/* To be compatible with the original U-Boot code:  in reset_cpu()
23 	 * addr: - 0: perform hard reset.  in reset_cpu()
24 	 *       - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */  in reset_cpu()
26 		/* Reset pulse length is 13005 peripheral clock frames */  in reset_cpu()
27 		writel(13000, &wdt->pulse);  in reset_cpu()
31 		       | WDTIM_MCTRL_M_RES2, &wdt->mctrl);  in reset_cpu()
34 		writel(0x01, &wdt->emr);  in reset_cpu()
36 		/* Internal reset on match output (no pulse on "RESOUT_N") */  in reset_cpu()
37 		writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);  in reset_cpu()
48 	 * It might be necessary to flush data cache, if U-Boot is loaded  in arch_cpu_init()