Lines Matching +full:spi +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
5 /dts-v1/;
8 #include "dt-bindings/clock/snps,hsdk-cgu.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
23 #clock-cells = <0>;
24 compatible = "fixed-clock";
25 clock-frequency = <500000000>;
26 u-boot,dm-pre-reloc;
30 clk-fmeas {
44 clock-names = "cpu-pll", "sys-pll",
45 "tun-pll", "ddr-clk",
46 "cpu-clk", "hdmi-pll",
47 "tun-clk", "hdmi-clk",
48 "apb-clk", "axi-clk",
49 "eth-clk", "usb-clk",
50 "sdio-clk", "hdmi-sys-clk",
51 "gfx-core-clk", "gfx-dma-clk",
52 "gfx-cfg-clk", "dmac-core-clk",
53 "dmac-cfg-clk", "sdio-ref-clk",
54 "spi-clk", "i2c-clk",
55 "uart-clk", "ebi-clk",
56 "rom-clk", "pwm-clk";
59 cgu_clk: cgu-clk@f0000000 {
60 compatible = "snps,hsdk-cgu-clock";
62 #clock-cells = <1>;
66 compatible = "snps,dw-apb-uart";
68 reg-shift = <2>;
69 reg-io-width = <4>;
73 #interrupt-cells = <1>;
74 compatible = "altr,socfpga-stmmac";
76 phy-mode = "gmii";
80 compatible = "generic-ehci";
85 compatible = "generic-ohci";
89 spi0: spi@f0020000 {
90 compatible = "snps,dw-apb-ssi";
92 #address-cells = <1>;
93 #size-cells = <0>;
94 spi-max-frequency = <4000000>;
96 clock-names = "spi_clk";
97 cs-gpio = <&cs_gpio 0>;
99 compatible = "spi-flash";
101 spi-max-frequency = <4000000>;
106 compatible = "snps,creg-gpio";
108 gpio-controller;
109 #gpio-cells = <1>;
110 gpio-bank-name = "hsdk-spi-cs";
111 gpio-count = <1>;
112 gpio-first-shift = <0>;
113 gpio-bit-per-line = <2>;
114 gpio-activate-val = <2>;
115 gpio-deactivate-val = <3>;
116 gpio-default-val = <1>;