Lines Matching refs:RCC_BASE_ADDR
17 #define RCC_BASE_ADDR 0x40021000 macro
119 qtest_writel(qts, (RCC_BASE_ADDR + A_CR), R_CR_MSION_MASK); in init_clocks()
122 qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); in init_clocks()
132 qtest_writel(qts, (RCC_BASE_ADDR + A_PLLCFGR), R_PLLCFGR_PLLREN_MASK | in init_clocks()
138 value = qtest_readl(qts, (RCC_BASE_ADDR + A_CR)); in init_clocks()
139 qtest_writel(qts, (RCC_BASE_ADDR + A_CR), value | R_CR_PLLON_MASK); in init_clocks()
142 qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), 0); in init_clocks()
145 qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0); in init_clocks()
148 value = qtest_readl(qts, (RCC_BASE_ADDR + A_CFGR)); in init_clocks()
149 qtest_writel(qts, (RCC_BASE_ADDR + A_CFGR), (value & ~R_CFGR_SW_MASK) | in init_clocks()
153 qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), R_APB2ENR_SYSCFGEN_MASK); in init_clocks()
156 qtest_writel(qts, (RCC_BASE_ADDR + A_AHB2ENR), R_AHB2ENR_GPIOBEN_MASK); in init_clocks()
160 qtest_writel(qts, (RCC_BASE_ADDR + A_APB2ENR), in init_clocks()
166 qtest_writel(qts, (RCC_BASE_ADDR + A_CCIPR), 0); in init_clocks()
169 qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 1 << 14); in init_clocks()
170 qtest_writel(qts, (RCC_BASE_ADDR + A_APB2RSTR), 0); in init_clocks()