Lines Matching refs:base_addr
161 static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank) in choose_bank() argument
163 uint8_t ctl3 = qtest_readb(qts, base_addr + OFFSET_CTL3); in choose_bank()
171 qtest_writeb(qts, base_addr + OFFSET_CTL3, ctl3); in choose_bank()
174 static void check_running(QTestState *qts, uint64_t base_addr) in check_running() argument
176 g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); in check_running()
177 g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); in check_running()
180 static void check_stopped(QTestState *qts, uint64_t base_addr) in check_stopped() argument
184 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); in check_stopped()
185 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY); in check_stopped()
186 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB); in check_stopped()
188 cst3 = qtest_readb(qts, base_addr + OFFSET_CST3); in check_stopped()
190 qtest_writeb(qts, base_addr + OFFSET_CST3, cst3); in check_stopped()
191 cst3 = qtest_readb(qts, base_addr + OFFSET_CST3); in check_stopped()
195 static void enable_bus(QTestState *qts, uint64_t base_addr) in enable_bus() argument
197 uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); in enable_bus()
200 qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); in enable_bus()
201 g_assert_true(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE); in enable_bus()
204 static void disable_bus(QTestState *qts, uint64_t base_addr) in disable_bus() argument
206 uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2); in disable_bus()
209 qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2); in disable_bus()
210 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE); in disable_bus()
213 static void start_transfer(QTestState *qts, uint64_t base_addr) in start_transfer() argument
218 qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); in start_transfer()
219 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, in start_transfer()
221 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, in start_transfer()
223 check_running(qts, base_addr); in start_transfer()
226 static void stop_transfer(QTestState *qts, uint64_t base_addr) in stop_transfer() argument
228 uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in stop_transfer()
232 qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); in stop_transfer()
233 ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in stop_transfer()
237 static void send_byte(QTestState *qts, uint64_t base_addr, uint8_t byte) in send_byte() argument
239 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, in send_byte()
241 qtest_writeb(qts, base_addr + OFFSET_SDA, byte); in send_byte()
244 static bool check_recv(QTestState *qts, uint64_t base_addr) in check_recv() argument
249 st = qtest_readb(qts, base_addr + OFFSET_ST); in check_recv()
250 choose_bank(qts, base_addr, 0); in check_recv()
251 fif_ctl = qtest_readb(qts, base_addr + OFFSET_FIF_CTL); in check_recv()
257 choose_bank(qts, base_addr, 1); in check_recv()
258 rxf_ctl = qtest_readb(qts, base_addr + OFFSET_RXF_CTL); in check_recv()
259 rxf_sts = qtest_readb(qts, base_addr + OFFSET_RXF_STS); in check_recv()
268 static uint8_t recv_byte(QTestState *qts, uint64_t base_addr) in recv_byte() argument
270 g_assert_true(check_recv(qts, base_addr)); in recv_byte()
271 return qtest_readb(qts, base_addr + OFFSET_SDA); in recv_byte()
274 static void send_address(QTestState *qts, uint64_t base_addr, uint8_t addr, in send_address() argument
280 qtest_writeb(qts, base_addr + OFFSET_SDA, encoded_addr); in send_address()
281 st = qtest_readb(qts, base_addr + OFFSET_ST); in send_address()
290 qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR); in send_address()
291 st = qtest_readb(qts, base_addr + OFFSET_ST); in send_address()
293 g_assert_true(check_recv(qts, base_addr)); in send_address()
306 static void send_nack(QTestState *qts, uint64_t base_addr) in send_nack() argument
308 uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1); in send_nack()
312 qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1); in send_nack()
315 static void start_fifo_mode(QTestState *qts, uint64_t base_addr) in start_fifo_mode() argument
317 choose_bank(qts, base_addr, 0); in start_fifo_mode()
318 qtest_writeb(qts, base_addr + OFFSET_FIF_CTL, FIF_CTL_FIFO_EN); in start_fifo_mode()
319 g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTL) & in start_fifo_mode()
321 choose_bank(qts, base_addr, 1); in start_fifo_mode()
322 qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, in start_fifo_mode()
324 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_FIF_CTS), ==, in start_fifo_mode()
326 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_TXF_STS), ==, 0); in start_fifo_mode()
327 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_RXF_STS), ==, 0); in start_fifo_mode()
330 static void start_recv_fifo(QTestState *qts, uint64_t base_addr, uint8_t bytes) in start_recv_fifo() argument
332 choose_bank(qts, base_addr, 1); in start_recv_fifo()
333 qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, 0); in start_recv_fifo()
334 qtest_writeb(qts, base_addr + OFFSET_RXF_CTL, in start_recv_fifo()
342 uint64_t base_addr = SMBUS_ADDR(index); in test_disable_bus() local
345 disable_bus(qts, base_addr); in test_disable_bus()
346 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, 0); in test_disable_bus()
347 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0); in test_disable_bus()
348 g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST3) & CST3_EO_BUSY); in test_disable_bus()
349 g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CST), ==, 0); in test_disable_bus()
357 uint64_t base_addr = SMBUS_ADDR(index); in test_invalid_addr() local
362 enable_bus(qts, base_addr); in test_invalid_addr()
364 start_transfer(qts, base_addr); in test_invalid_addr()
365 send_address(qts, base_addr, INVALID_DEVICE_ADDR, false, false); in test_invalid_addr()
367 stop_transfer(qts, base_addr); in test_invalid_addr()
368 check_running(qts, base_addr); in test_invalid_addr()
369 qtest_writeb(qts, base_addr + OFFSET_ST, ST_NEGACK); in test_invalid_addr()
370 g_assert_false(qtest_readb(qts, base_addr + OFFSET_ST) & ST_NEGACK); in test_invalid_addr()
371 check_stopped(qts, base_addr); in test_invalid_addr()
379 uint64_t base_addr = SMBUS_ADDR(index); in test_single_mode() local
385 enable_bus(qts, base_addr); in test_single_mode()
389 start_transfer(qts, base_addr); in test_single_mode()
391 send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); in test_single_mode()
392 send_byte(qts, base_addr, TMP105_REG_CONFIG); in test_single_mode()
393 send_byte(qts, base_addr, value); in test_single_mode()
394 stop_transfer(qts, base_addr); in test_single_mode()
395 check_stopped(qts, base_addr); in test_single_mode()
398 start_transfer(qts, base_addr); in test_single_mode()
399 send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); in test_single_mode()
400 send_byte(qts, base_addr, TMP105_REG_CONFIG); in test_single_mode()
401 start_transfer(qts, base_addr); in test_single_mode()
402 send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); in test_single_mode()
403 send_nack(qts, base_addr); in test_single_mode()
404 stop_transfer(qts, base_addr); in test_single_mode()
405 check_running(qts, base_addr); in test_single_mode()
406 g_assert_cmphex(recv_byte(qts, base_addr), ==, value); in test_single_mode()
407 check_stopped(qts, base_addr); in test_single_mode()
415 uint64_t base_addr = SMBUS_ADDR(index); in test_fifo_mode() local
421 enable_bus(qts, base_addr); in test_fifo_mode()
422 start_fifo_mode(qts, base_addr); in test_fifo_mode()
426 start_transfer(qts, base_addr); in test_fifo_mode()
427 send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); in test_fifo_mode()
428 choose_bank(qts, base_addr, 1); in test_fifo_mode()
429 g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & in test_fifo_mode()
431 qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, TXF_CTL_THR_TXIE); in test_fifo_mode()
432 send_byte(qts, base_addr, TMP105_REG_CONFIG); in test_fifo_mode()
433 send_byte(qts, base_addr, value); in test_fifo_mode()
434 g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & in test_fifo_mode()
436 g_assert_true(qtest_readb(qts, base_addr + OFFSET_TXF_STS) & in test_fifo_mode()
439 qtest_readb(qts, base_addr + OFFSET_TXF_STS)), ==, 0); in test_fifo_mode()
441 stop_transfer(qts, base_addr); in test_fifo_mode()
442 check_stopped(qts, base_addr); in test_fifo_mode()
445 start_fifo_mode(qts, base_addr); in test_fifo_mode()
446 start_transfer(qts, base_addr); in test_fifo_mode()
447 send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true); in test_fifo_mode()
448 send_byte(qts, base_addr, TMP105_REG_CONFIG); in test_fifo_mode()
449 start_transfer(qts, base_addr); in test_fifo_mode()
450 qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, FIF_CTS_RXF_TXE); in test_fifo_mode()
451 start_recv_fifo(qts, base_addr, 1); in test_fifo_mode()
452 send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true); in test_fifo_mode()
453 g_assert_false(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) & in test_fifo_mode()
455 g_assert_true(qtest_readb(qts, base_addr + OFFSET_RXF_STS) & in test_fifo_mode()
458 qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 1); in test_fifo_mode()
459 send_nack(qts, base_addr); in test_fifo_mode()
460 stop_transfer(qts, base_addr); in test_fifo_mode()
461 check_running(qts, base_addr); in test_fifo_mode()
462 g_assert_cmphex(recv_byte(qts, base_addr), ==, value); in test_fifo_mode()
464 qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 0); in test_fifo_mode()
465 check_stopped(qts, base_addr); in test_fifo_mode()