Lines Matching refs:g_assert_cmpint
56 g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086); in test_i440fx_defaults()
58 g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237); in test_i440fx_defaults()
61 g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006); in test_i440fx_defaults()
63 g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280); in test_i440fx_defaults()
66 g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00); in test_i440fx_defaults()
67 g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600); in test_i440fx_defaults()
69 g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00); in test_i440fx_defaults()
71 g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00); in test_i440fx_defaults()
73 g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00); in test_i440fx_defaults()
86 g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */ in test_i440fx_defaults()
89 g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */ in test_i440fx_defaults()
92 g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */ in test_i440fx_defaults()
94 g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */ in test_i440fx_defaults()
97 g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */ in test_i440fx_defaults()
99 g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */ in test_i440fx_defaults()
102 g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */ in test_i440fx_defaults()
103 g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */ in test_i440fx_defaults()
104 g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */ in test_i440fx_defaults()
105 g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */ in test_i440fx_defaults()
106 g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */ in test_i440fx_defaults()
107 g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */ in test_i440fx_defaults()
108 g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */ in test_i440fx_defaults()
111 g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */ in test_i440fx_defaults()
112 g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */ in test_i440fx_defaults()
113 g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */ in test_i440fx_defaults()
114 g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */ in test_i440fx_defaults()
115 g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */ in test_i440fx_defaults()
116 g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */ in test_i440fx_defaults()
117 g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */ in test_i440fx_defaults()
118 g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */ in test_i440fx_defaults()
121 g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */ in test_i440fx_defaults()
123 g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */ in test_i440fx_defaults()
126 g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */ in test_i440fx_defaults()
129 g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */ in test_i440fx_defaults()
131 g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */ in test_i440fx_defaults()
133 g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */ in test_i440fx_defaults()
135 g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */ in test_i440fx_defaults()