Lines Matching +full:asi +full:- +full:format
4 * Copyright (c) 2003-2005 Fabrice Bellard
25 #include "exec/helper-proto.h"
26 #include "exec/exec-all.h"
28 #include "exec/page-protection.h"
31 #include "user/page-protection.h"
33 #include "asi.h"
57 do { printf("ASI: " fmt , ## __VA_ARGS__); } while (0)
69 #define AM_CHECK(env1) ((env1)->pstate & PS_AM)
86 int ctx = mmu->tag_access & 0x1fffULL; in ultrasparc_tsb_pointer()
87 uint64_t ctx_register = mmu->sun4v_ctx_config[ctx ? 1 : 0]; in ultrasparc_tsb_pointer()
92 tsb_register = mmu->sun4v_tsb_pointers[tsb_index]; in ultrasparc_tsb_pointer()
95 tsb_register = mmu->tsb; in ultrasparc_tsb_pointer()
104 uint64_t va = mmu->tag_access >> (3 * page_size + 9); in ultrasparc_tsb_pointer()
133 if (TTE_IS_VALID(tlb->tte)) { in replace_tlb_entry()
136 size = 8192ULL << 3 * TTE_PGSIZE(tlb->tte); in replace_tlb_entry()
139 va = tlb->tag & mask; in replace_tlb_entry()
146 tlb->tag = tlb_tag; in replace_tlb_entry()
147 tlb->tte = tlb_tte; in replace_tlb_entry()
162 context = env1->dmmu.mmu_primary_context; in demap_tlb()
165 context = env1->dmmu.mmu_secondary_context; in demap_tlb()
179 /* will remove non-global entries matching context value */ in demap_tlb()
215 /* is already in the sun4u format */ in sun4v_tte_to_sun4u()
249 DPRINTF_MMU("auto demap entry [%d] %lx->%lx\n", i, vaddr, in replace_tlb_1bit_lru()
307 /* returns true if access using this ASI is to have address translated by MMU
310 static inline int is_translating_asi(int asi) in is_translating_asi() argument
312 /* Ultrasparc IIi translating asi in is_translating_asi()
313 - note this list is defined by cpu implementation in is_translating_asi()
315 switch (asi) { in is_translating_asi()
339 int asi, target_ulong addr) in asi_address_mask() argument
341 if (is_translating_asi(asi)) { in asi_address_mask()
348 static inline void do_check_asi(CPUSPARCState *env, int asi, uintptr_t ra) in do_check_asi() argument
354 if (asi < 0x80 in do_check_asi()
357 || (asi >= 0x30 && cpu_has_hypervisor(env)))) { in do_check_asi()
380 env->mxccdata[0], env->mxccdata[1], in dump_mxcc()
381 env->mxccdata[2], env->mxccdata[3]); in dump_mxcc()
386 env->mxccregs[0], env->mxccregs[1], in dump_mxcc()
387 env->mxccregs[2], env->mxccregs[3], in dump_mxcc()
388 env->mxccregs[4], env->mxccregs[5], in dump_mxcc()
389 env->mxccregs[6], env->mxccregs[7]); in dump_mxcc()
395 static void dump_asi(const char *txt, target_ulong addr, int asi, int size, in dump_asi() argument
400 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %02" PRIx64 "\n", txt, in dump_asi()
401 addr, asi, r1 & 0xff); in dump_asi()
404 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %04" PRIx64 "\n", txt, in dump_asi()
405 addr, asi, r1 & 0xffff); in dump_asi()
408 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %08" PRIx64 "\n", txt, in dump_asi()
409 addr, asi, r1 & 0xffffffff); in dump_asi()
412 DPRINTF_ASI("%s "TARGET_FMT_lx " asi 0x%02x = %016" PRIx64 "\n", txt, in dump_asi()
413 addr, asi, r1); in dump_asi()
431 " asi 0x%02x from " TARGET_FMT_lx "\n", in sparc_raise_mmu_fault()
433 size == 1 ? "" : "s", addr, is_asi, env->pc); in sparc_raise_mmu_fault()
438 size == 1 ? "" : "s", addr, env->pc); in sparc_raise_mmu_fault()
442 fault_type = (env->mmuregs[3] & 0x1c) >> 2; in sparc_raise_mmu_fault()
444 env->mmuregs[3] = 0; /* Fault status register */ in sparc_raise_mmu_fault()
446 env->mmuregs[3] |= 1 << 16; in sparc_raise_mmu_fault()
448 if (env->psrs) { in sparc_raise_mmu_fault()
449 env->mmuregs[3] |= 1 << 5; in sparc_raise_mmu_fault()
452 env->mmuregs[3] |= 1 << 6; in sparc_raise_mmu_fault()
455 env->mmuregs[3] |= 1 << 7; in sparc_raise_mmu_fault()
457 env->mmuregs[3] |= (5 << 2) | 2; in sparc_raise_mmu_fault()
460 env->mmuregs[4] = addr; /* Fault address register */ in sparc_raise_mmu_fault()
464 if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { in sparc_raise_mmu_fault()
465 env->mmuregs[3] |= 1; in sparc_raise_mmu_fault()
468 if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { in sparc_raise_mmu_fault()
474 * flush neverland mappings created during no-fault mode, in sparc_raise_mmu_fault()
477 if (env->mmuregs[0] & MMU_NF) { in sparc_raise_mmu_fault()
490 "\n", addr, env->pc); in sparc_raise_mmu_fault()
494 if (env->lsu & (IMMU_E)) { in sparc_raise_mmu_fault()
496 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { in sparc_raise_mmu_fault()
500 if (env->lsu & (DMMU_E)) { in sparc_raise_mmu_fault()
502 } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { in sparc_raise_mmu_fault()
537 env->cache_control = val; in leon3_cache_control_st()
561 ret = env->cache_control; in leon3_cache_control_ld()
583 int asi, uint32_t memop) in helper_ld_asi() argument
593 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
594 switch (asi) { in helper_ld_asi()
601 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { in helper_ld_asi()
610 ret = env->mxccregs[3]; in helper_ld_asi()
619 ret = env->mxccregs[3]; in helper_ld_asi()
628 ret = env->mxccregs[5]; in helper_ld_asi()
638 ret = env->mxccregs[7]; in helper_ld_asi()
651 DPRINTF_MXCC("asi = %d, size = %d, sign = %d, " in helper_ld_asi()
652 "addr = %08x -> ret = %" PRIx64 "," in helper_ld_asi()
653 "addr = %08x\n", asi, size, sign, last_addr, ret, addr); in helper_ld_asi()
669 DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08" PRIx64 "\n", in helper_ld_asi()
678 ret = env->mmuregs[reg]; in helper_ld_asi()
680 env->mmuregs[3] = 0; in helper_ld_asi()
682 ret = env->mmuregs[3]; in helper_ld_asi()
684 ret = env->mmuregs[4]; in helper_ld_asi()
693 case ASI_M_TXTC_TAG: /* SparcStation 5 I-cache tag */ in helper_ld_asi()
694 case ASI_M_TXTC_DATA: /* SparcStation 5 I-cache data */ in helper_ld_asi()
695 case ASI_M_DATAC_TAG: /* SparcStation 5 D-cache tag */ in helper_ld_asi()
696 case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ in helper_ld_asi()
701 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); in helper_ld_asi()
705 ret = address_space_ldub(cs->as, access_addr, in helper_ld_asi()
709 ret = address_space_lduw(cs->as, access_addr, in helper_ld_asi()
714 ret = address_space_ldl(cs->as, access_addr, in helper_ld_asi()
718 ret = address_space_ldq(cs->as, access_addr, in helper_ld_asi()
741 ret = env->mmubpregs[reg]; in helper_ld_asi()
744 ret = env->mmubpregs[reg]; in helper_ld_asi()
747 ret = env->mmubpregs[reg]; in helper_ld_asi()
750 ret = env->mmubpregs[reg]; in helper_ld_asi()
751 env->mmubpregs[reg] = 0ULL; in helper_ld_asi()
759 ret = env->mmubpctrv; in helper_ld_asi()
762 ret = env->mmubpctrc; in helper_ld_asi()
765 ret = env->mmubpctrs; in helper_ld_asi()
768 ret = env->mmubpaction; in helper_ld_asi()
771 sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); in helper_ld_asi()
801 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
807 int asi, uint32_t memop) in helper_st_asi() argument
812 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
813 switch (asi) { in helper_st_asi()
820 if (env->def.features & CPU_FEATURE_CACHE_CTRL) { in helper_st_asi()
830 env->mxccdata[0] = val; in helper_st_asi()
839 env->mxccdata[1] = val; in helper_st_asi()
848 env->mxccdata[2] = val; in helper_st_asi()
857 env->mxccdata[3] = val; in helper_st_asi()
869 env->mxccregs[0] = val; in helper_st_asi()
878 hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; in helper_st_asi()
880 env->mxccdata[i] = address_space_ldq(cs->as, in helper_st_asi()
897 env->mxccregs[1] = val; in helper_st_asi()
906 hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; in helper_st_asi()
908 address_space_stq(cs->as, access_addr, env->mxccdata[i], in helper_st_asi()
921 env->mxccregs[3] = val; in helper_st_asi()
930 env->mxccregs[3] = (env->mxccregs[3] & 0xffffffff00000000ULL) in helper_st_asi()
941 env->mxccregs[6] &= ~val; in helper_st_asi()
950 env->mxccregs[7] = val; in helper_st_asi()
963 DPRINTF_MXCC("asi = %d, size = %d, addr = %08x, val = %" PRIx64 "\n", in helper_st_asi()
964 asi, size, addr, val); in helper_st_asi()
1000 oldreg = env->mmuregs[reg]; in helper_st_asi()
1003 env->mmuregs[reg] = (env->mmuregs[reg] & 0xff000000) | in helper_st_asi()
1005 /* Mappings generated during no-fault mode in helper_st_asi()
1007 if ((oldreg ^ env->mmuregs[reg]) in helper_st_asi()
1008 & (MMU_NF | env->def.mmu_bm)) { in helper_st_asi()
1013 env->mmuregs[reg] = val & env->def.mmu_ctpr_mask; in helper_st_asi()
1016 env->mmuregs[reg] = val & env->def.mmu_cxr_mask; in helper_st_asi()
1017 if (oldreg != env->mmuregs[reg]) { in helper_st_asi()
1027 env->mmuregs[reg] = val & env->def.mmu_trcr_mask; in helper_st_asi()
1031 env->mmuregs[3] = val & env->def.mmu_sfsr_mask; in helper_st_asi()
1034 env->mmuregs[4] = val; in helper_st_asi()
1037 env->mmuregs[reg] = val; in helper_st_asi()
1040 if (oldreg != env->mmuregs[reg]) { in helper_st_asi()
1041 DPRINTF_MMU("mmu change reg[%d]: 0x%08x -> 0x%08x\n", in helper_st_asi()
1042 reg, oldreg, env->mmuregs[reg]); in helper_st_asi()
1053 case ASI_M_TXTC_TAG: /* I-cache tag */ in helper_st_asi()
1054 case ASI_M_TXTC_DATA: /* I-cache data */ in helper_st_asi()
1055 case ASI_M_DATAC_TAG: /* D-cache tag */ in helper_st_asi()
1056 case ASI_M_DATAC_DATA: /* D-cache data */ in helper_st_asi()
1057 case ASI_M_FLUSH_PAGE: /* I/D-cache flush page */ in helper_st_asi()
1058 case ASI_M_FLUSH_SEG: /* I/D-cache flush segment */ in helper_st_asi()
1059 case ASI_M_FLUSH_REGION: /* I/D-cache flush region */ in helper_st_asi()
1060 case ASI_M_FLUSH_CTX: /* I/D-cache flush context */ in helper_st_asi()
1061 case ASI_M_FLUSH_USER: /* I/D-cache flush user */ in helper_st_asi()
1066 hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); in helper_st_asi()
1070 address_space_stb(cs->as, access_addr, val, in helper_st_asi()
1074 address_space_stw(cs->as, access_addr, val, in helper_st_asi()
1079 address_space_stl(cs->as, access_addr, val, in helper_st_asi()
1083 address_space_stq(cs->as, access_addr, val, in helper_st_asi()
1094 case 0x31: /* store buffer data, Ross RT620 I-cache flush or in helper_st_asi()
1098 case 0x36: /* I-cache flash clear */ in helper_st_asi()
1099 case 0x37: /* D-cache flash clear */ in helper_st_asi()
1107 env->mmubpregs[reg] = (val & 0xfffffffffULL); in helper_st_asi()
1110 env->mmubpregs[reg] = (val & 0xfffffffffULL); in helper_st_asi()
1113 env->mmubpregs[reg] = (val & 0x7fULL); in helper_st_asi()
1116 env->mmubpregs[reg] = (val & 0xfULL); in helper_st_asi()
1120 env->mmuregs[reg]); in helper_st_asi()
1124 env->mmubpctrv = val & 0xffffffff; in helper_st_asi()
1127 env->mmubpctrc = val & 0x3; in helper_st_asi()
1130 env->mmubpctrs = val & 0x3; in helper_st_asi()
1133 env->mmubpaction = val & 0x1fff; in helper_st_asi()
1138 sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); in helper_st_asi()
1152 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1204 int asi, uint32_t memop) in helper_ld_asi() argument
1210 if (asi < 0x80) { in helper_ld_asi()
1213 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
1214 addr = asi_address_mask(env, asi, addr); in helper_ld_asi()
1216 switch (asi) { in helper_ld_asi()
1217 case ASI_PNF: /* Primary no-fault */ in helper_ld_asi()
1218 case ASI_PNFL: /* Primary no-fault LE */ in helper_ld_asi()
1219 case ASI_SNF: /* Secondary no-fault */ in helper_ld_asi()
1220 case ASI_SNFL: /* Secondary no-fault LE */ in helper_ld_asi()
1256 switch (asi) { in helper_ld_asi()
1257 case ASI_PNFL: /* Primary no-fault LE */ in helper_ld_asi()
1258 case ASI_SNFL: /* Secondary no-fault LE */ in helper_ld_asi()
1287 dump_asi("read", addr, asi, size, ret); in helper_ld_asi()
1293 int asi, uint32_t memop) in helper_st_asi() argument
1297 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1299 if (asi < 0x80) { in helper_st_asi()
1302 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
1304 switch (asi) { in helper_st_asi()
1312 case ASI_PNF: /* Primary no-fault, RO */ in helper_st_asi()
1313 case ASI_SNF: /* Secondary no-fault, RO */ in helper_st_asi()
1314 case ASI_PNFL: /* Primary no-fault LE, RO */ in helper_st_asi()
1315 case ASI_SNFL: /* Secondary no-fault LE, RO */ in helper_st_asi()
1324 int asi, uint32_t memop) in helper_ld_asi() argument
1334 asi &= 0xff; in helper_ld_asi()
1336 do_check_asi(env, asi, GETPC()); in helper_ld_asi()
1337 do_check_align(env, addr, size - 1, GETPC()); in helper_ld_asi()
1338 addr = asi_address_mask(env, asi, addr); in helper_ld_asi()
1340 switch (asi) { in helper_ld_asi()
1347 int idx = (env->pstate & PS_PRIV in helper_ld_asi()
1348 ? (asi & 1 ? MMU_KERNEL_SECONDARY_IDX : MMU_KERNEL_IDX) in helper_ld_asi()
1349 : (asi & 1 ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX)); in helper_ld_asi()
1351 if (cpu_get_phys_page_nofault(env, addr, idx) == -1ULL) { in helper_ld_asi()
1353 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
1356 cpu_raise_exception_ra(env, cs->exception_index, GETPC()); in helper_ld_asi()
1387 case ASI_REAL_IO: /* Bypass, non-cacheable */ in helper_ld_asi()
1389 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ in helper_ld_asi()
1418 ret = env->lsu; in helper_ld_asi()
1420 case ASI_IMMU: /* I-MMU regs */ in helper_ld_asi()
1425 /* 0x00 I-TSB Tag Target register */ in helper_ld_asi()
1426 ret = ultrasparc_tag_target(env->immu.tag_access); in helper_ld_asi()
1429 ret = env->immu.sfsr; in helper_ld_asi()
1432 ret = env->immu.tsb; in helper_ld_asi()
1435 /* 0x30 I-TSB Tag Access register */ in helper_ld_asi()
1436 ret = env->immu.tag_access; in helper_ld_asi()
1444 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer */ in helper_ld_asi()
1446 /* env->immuregs[5] holds I-MMU TSB register value in helper_ld_asi()
1447 env->immuregs[6] holds I-MMU Tag Access register value */ in helper_ld_asi()
1448 ret = ultrasparc_tsb_pointer(env, &env->immu, 0); in helper_ld_asi()
1451 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer */ in helper_ld_asi()
1453 /* env->immuregs[5] holds I-MMU TSB register value in helper_ld_asi()
1454 env->immuregs[6] holds I-MMU Tag Access register value */ in helper_ld_asi()
1455 ret = ultrasparc_tsb_pointer(env, &env->immu, 1); in helper_ld_asi()
1458 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ in helper_ld_asi()
1462 ret = env->itlb[reg].tte; in helper_ld_asi()
1465 case ASI_ITLB_TAG_READ: /* I-MMU tag read */ in helper_ld_asi()
1469 ret = env->itlb[reg].tag; in helper_ld_asi()
1472 case ASI_DMMU: /* D-MMU regs */ in helper_ld_asi()
1477 /* 0x00 D-TSB Tag Target register */ in helper_ld_asi()
1478 ret = ultrasparc_tag_target(env->dmmu.tag_access); in helper_ld_asi()
1481 ret = env->dmmu.mmu_primary_context; in helper_ld_asi()
1484 ret = env->dmmu.mmu_secondary_context; in helper_ld_asi()
1487 ret = env->dmmu.sfsr; in helper_ld_asi()
1490 ret = env->dmmu.sfar; in helper_ld_asi()
1493 ret = env->dmmu.tsb; in helper_ld_asi()
1495 case 6: /* 0x30 D-TSB Tag Access register */ in helper_ld_asi()
1496 ret = env->dmmu.tag_access; in helper_ld_asi()
1499 ret = env->dmmu.virtual_watchpoint; in helper_ld_asi()
1502 ret = env->dmmu.physical_watchpoint; in helper_ld_asi()
1510 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer */ in helper_ld_asi()
1512 /* env->dmmuregs[5] holds D-MMU TSB register value in helper_ld_asi()
1513 env->dmmuregs[6] holds D-MMU Tag Access register value */ in helper_ld_asi()
1514 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 0); in helper_ld_asi()
1517 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer */ in helper_ld_asi()
1519 /* env->dmmuregs[5] holds D-MMU TSB register value in helper_ld_asi()
1520 env->dmmuregs[6] holds D-MMU Tag Access register value */ in helper_ld_asi()
1521 ret = ultrasparc_tsb_pointer(env, &env->dmmu, 1); in helper_ld_asi()
1524 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ in helper_ld_asi()
1528 ret = env->dtlb[reg].tte; in helper_ld_asi()
1531 case ASI_DTLB_TAG_READ: /* D-MMU tag read */ in helper_ld_asi()
1535 ret = env->dtlb[reg].tag; in helper_ld_asi()
1541 ret = env->ivec_status; in helper_ld_asi()
1547 ret = env->ivec_data[reg]; in helper_ld_asi()
1560 ret = env->scratch[i]; in helper_ld_asi()
1566 ret = env->dmmu.mmu_primary_context; in helper_ld_asi()
1569 ret = env->dmmu.mmu_secondary_context; in helper_ld_asi()
1575 case ASI_DCACHE_DATA: /* D-cache data */ in helper_ld_asi()
1576 case ASI_DCACHE_TAG: /* D-cache tag access */ in helper_ld_asi()
1577 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ in helper_ld_asi()
1578 case ASI_AFSR: /* E-cache asynchronous fault status */ in helper_ld_asi()
1579 case ASI_AFAR: /* E-cache asynchronous fault address */ in helper_ld_asi()
1580 case ASI_EC_TAG_DATA: /* E-cache tag data */ in helper_ld_asi()
1581 case ASI_IC_INSTR: /* I-cache instruction access */ in helper_ld_asi()
1582 case ASI_IC_TAG: /* I-cache tag access */ in helper_ld_asi()
1583 case ASI_IC_PRE_DECODE: /* I-cache predecode */ in helper_ld_asi()
1584 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ in helper_ld_asi()
1585 case ASI_EC_W: /* E-cache tag */ in helper_ld_asi()
1586 case ASI_EC_R: /* E-cache tag */ in helper_ld_asi()
1588 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer */ in helper_ld_asi()
1589 case ASI_ITLB_DATA_IN: /* I-MMU data in, WO */ in helper_ld_asi()
1590 case ASI_IMMU_DEMAP: /* I-MMU demap, WO */ in helper_ld_asi()
1591 case ASI_DTLB_DATA_IN: /* D-MMU data in, WO */ in helper_ld_asi()
1592 case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ in helper_ld_asi()
1617 dump_asi("read ", last_addr, asi, size, ret); in helper_ld_asi()
1623 int asi, uint32_t memop) in helper_st_asi() argument
1629 dump_asi("write", addr, asi, size, val); in helper_st_asi()
1632 asi &= 0xff; in helper_st_asi()
1634 do_check_asi(env, asi, GETPC()); in helper_st_asi()
1635 do_check_align(env, addr, size - 1, GETPC()); in helper_st_asi()
1636 addr = asi_address_mask(env, asi, addr); in helper_st_asi()
1638 switch (asi) { in helper_st_asi()
1648 case ASI_REAL_IO: /* Bypass, non-cacheable */ in helper_st_asi()
1650 case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */ in helper_st_asi()
1670 /* these ASIs have different functions on UltraSPARC-IIIi in helper_st_asi()
1684 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); in helper_st_asi()
1685 env->dmmu.sun4v_tsb_pointers[idx] = val; in helper_st_asi()
1697 env->dmmu.sun4v_ctx_config[(asi & 8) >> 3] = val; in helper_st_asi()
1713 int idx = ((asi & 2) >> 1) | ((asi & 8) >> 2); in helper_st_asi()
1714 env->immu.sun4v_tsb_pointers[idx] = val; in helper_st_asi()
1726 env->immu.sun4v_ctx_config[(asi & 8) >> 3] = val; in helper_st_asi()
1735 env->lsu = val & (DMMU_E | IMMU_E); in helper_st_asi()
1737 case ASI_IMMU: /* I-MMU regs */ in helper_st_asi()
1742 oldreg = env->immu.mmuregs[reg]; in helper_st_asi()
1746 case 1: /* Not in I-MMU */ in helper_st_asi()
1753 env->immu.sfsr = val; in helper_st_asi()
1758 DPRINTF_MMU("immu TSB write: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1759 PRIx64 "\n", env->immu.tsb, val); in helper_st_asi()
1760 env->immu.tsb = val; in helper_st_asi()
1763 env->immu.tag_access = val; in helper_st_asi()
1773 if (oldreg != env->immu.mmuregs[reg]) { in helper_st_asi()
1774 DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1775 PRIx64 "\n", reg, oldreg, env->immuregs[reg]); in helper_st_asi()
1782 case ASI_ITLB_DATA_IN: /* I-MMU data in */ in helper_st_asi()
1785 replace_tlb_1bit_lru(env->itlb, env->immu.tag_access, in helper_st_asi()
1789 case ASI_ITLB_DATA_ACCESS: /* I-MMU data access */ in helper_st_asi()
1797 replace_tlb_entry(&env->itlb[i], env->immu.tag_access, in helper_st_asi()
1806 case ASI_IMMU_DEMAP: /* I-MMU demap */ in helper_st_asi()
1807 demap_tlb(env->itlb, addr, "immu", env); in helper_st_asi()
1809 case ASI_DMMU: /* D-MMU regs */ in helper_st_asi()
1814 oldreg = env->dmmu.mmuregs[reg]; in helper_st_asi()
1822 env->dmmu.sfar = 0; in helper_st_asi()
1824 env->dmmu.sfsr = val; in helper_st_asi()
1827 env->dmmu.mmu_primary_context = val; in helper_st_asi()
1833 env->dmmu.mmu_secondary_context = val; in helper_st_asi()
1839 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1840 PRIx64 "\n", env->dmmu.tsb, val); in helper_st_asi()
1841 env->dmmu.tsb = val; in helper_st_asi()
1844 env->dmmu.tag_access = val; in helper_st_asi()
1847 env->dmmu.virtual_watchpoint = val; in helper_st_asi()
1850 env->dmmu.physical_watchpoint = val; in helper_st_asi()
1857 if (oldreg != env->dmmu.mmuregs[reg]) { in helper_st_asi()
1858 DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016" in helper_st_asi()
1859 PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]); in helper_st_asi()
1866 case ASI_DTLB_DATA_IN: /* D-MMU data in */ in helper_st_asi()
1869 replace_tlb_1bit_lru(env->dtlb, env->dmmu.tag_access, in helper_st_asi()
1873 case ASI_DTLB_DATA_ACCESS: /* D-MMU data access */ in helper_st_asi()
1879 replace_tlb_entry(&env->dtlb[i], env->dmmu.tag_access, in helper_st_asi()
1888 case ASI_DMMU_DEMAP: /* D-MMU demap */ in helper_st_asi()
1889 demap_tlb(env->dtlb, addr, "dmmu", env); in helper_st_asi()
1892 env->ivec_status = val & 0x20; in helper_st_asi()
1903 env->scratch[i] = val; in helper_st_asi()
1910 env->dmmu.mmu_primary_context = val; in helper_st_asi()
1911 env->immu.mmu_primary_context = val; in helper_st_asi()
1916 env->dmmu.mmu_secondary_context = val; in helper_st_asi()
1917 env->immu.mmu_secondary_context = val; in helper_st_asi()
1928 case ASI_DCACHE_DATA: /* D-cache data */ in helper_st_asi()
1929 case ASI_DCACHE_TAG: /* D-cache tag access */ in helper_st_asi()
1930 case ASI_ESTATE_ERROR_EN: /* E-cache error enable */ in helper_st_asi()
1931 case ASI_AFSR: /* E-cache asynchronous fault status */ in helper_st_asi()
1932 case ASI_AFAR: /* E-cache asynchronous fault address */ in helper_st_asi()
1933 case ASI_EC_TAG_DATA: /* E-cache tag data */ in helper_st_asi()
1934 case ASI_IC_INSTR: /* I-cache instruction access */ in helper_st_asi()
1935 case ASI_IC_TAG: /* I-cache tag access */ in helper_st_asi()
1936 case ASI_IC_PRE_DECODE: /* I-cache predecode */ in helper_st_asi()
1937 case ASI_IC_NEXT_FIELD: /* I-cache LRU etc. */ in helper_st_asi()
1938 case ASI_EC_W: /* E-cache tag */ in helper_st_asi()
1939 case ASI_EC_R: /* E-cache tag */ in helper_st_asi()
1941 case ASI_IMMU_TSB_8KB_PTR: /* I-MMU 8k TSB pointer, RO */ in helper_st_asi()
1942 case ASI_IMMU_TSB_64KB_PTR: /* I-MMU 64k TSB pointer, RO */ in helper_st_asi()
1943 case ASI_ITLB_TAG_READ: /* I-MMU tag read, RO */ in helper_st_asi()
1944 case ASI_DMMU_TSB_8KB_PTR: /* D-MMU 8k TSB pointer, RO */ in helper_st_asi()
1945 case ASI_DMMU_TSB_64KB_PTR: /* D-MMU 64k TSB pointer, RO */ in helper_st_asi()
1946 case ASI_DMMU_TSB_DIRECT_PTR: /* D-MMU data pointer, RO */ in helper_st_asi()
1947 case ASI_DTLB_TAG_READ: /* D-MMU tag read, RO */ in helper_st_asi()
1950 case ASI_PNF: /* Primary no-fault, RO */ in helper_st_asi()
1951 case ASI_SNF: /* Secondary no-fault, RO */ in helper_st_asi()
1952 case ASI_PNFL: /* Primary no-fault LE, RO */ in helper_st_asi()
1953 case ASI_SNFL: /* Secondary no-fault LE, RO */ in helper_st_asi()