target/sparc/cpu.h

5 #include "cpu-qom.h"
6 #include "exec/cpu-defs.h"
7 #include "qemu/cpu-float.h"
244 #include "cpu-feature.h.inc"
251 #include "cpu-feature.h.inc"
316 #define TLB_UST1_IS_SUN4V_BIT  (1ULL << 10) /* sun4u/sun4v TTE format switch */
323 #define SFSR_FT_ILL_BIT     (1ULL << 10)   /* illegal LDA/STA ASI */
332 #define SFSR_ASI_SHIFT      16             /* 23:16 ASI value */
417      * Z is represented as == 0; any non-zero value is !Z.
418      * For sparc64, the high 32-bits of icc.Z are garbage.
445      * Single-element FPU fault queue, with address and insn,
446      * packaged into the double-word with which it is stored.
513 #define MAXTL_MASK (MAXTL_MAX - 1)
515     uint32_t asi;  member
643 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
648     return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);  in tlb_compare_context()
653 /* cpu-exec.c */
687     return env1->def.features & CPU_FEATURE_HYPV;  in cpu_has_hypervisor()
692     return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);  in cpu_hypervisor_mode()
697     return env1->pstate & PS_PRIV;  in cpu_supervisor_mode()
702     return env1->psrs;  in cpu_supervisor_mode()
709     if (env1->psret != 0)  in cpu_interrupts_enabled()
712     if ((env1->pstate & PS_IE) && !cpu_hypervisor_mode(env1)) {  in cpu_interrupts_enabled()
723     /* level 15 is non-maskable on sparc v8 */  in cpu_pil_allowed()
724     return pil == 15 || pil > env1->psrpil;  in cpu_pil_allowed()
726     return pil > env1->psrpil;  in cpu_pil_allowed()
730 #include "exec/cpu-all.h"
779         ((env->asi & 0xff) << 24) | ((env->pstate & 0xf3f) << 8) |  in sparc64_tstate()
782     if (env->def.features & CPU_FEATURE_GL) {  in sparc64_tstate()
783         tstate |= (env->gl & 7ULL) << 40;  in sparc64_tstate()