Lines Matching +full:wo +full:- +full:data

36 /* SPARCstation-5: only 6 bits are decoded. */
37 /* wo = Write Only, rw = Read Write; */
52 #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
53 #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
54 #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
62 #define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
63 #define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
64 #define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
65 #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
66 #define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
68 /* Block-copy operations are available only on certain V8 cpus. */
72 #define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
73 #define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
74 #define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
75 #define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
76 #define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
78 /* Block-fill operations are available on certain V8 cpus */
82 * the available ASI's for physical ram pass-through, but I don't have
88 #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
89 #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
90 #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
91 #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
97 #define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
103 #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
136 #define ASI_PL 0x88 /* Primary, implicit, l-endian */
137 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
138 #define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
139 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
142 * UltraSparc-III and later specific ASIs. The "(CMT)" marker designates
144 * ASIs, "(4V)" designates SUN4V specific ASIs. "(NG4)" designates SPARC-T4
150 #define ASI_PHYS_USE_EC 0x14 /* PADDR, E-cacheable */
151 #define ASI_REAL_IO 0x15 /* Real address, non-cacheable */
152 #define ASI_PHYS_BYPASS_EC_E 0x15 /* PADDR, E-bit */
156 #define ASI_PHYS_USE_EC_L 0x1c /* PADDR, E-cacheable, little endian*/
157 #define ASI_REAL_IO_L 0x1d /* Real address, non-cacheable, LE */
158 #define ASI_PHYS_BYPASS_EC_E_L 0x1d /* PADDR, E-bit, little endian */
159 #define ASI_BLK_AIUP_L_4V 0x1e /* (4V) Prim, user, block, l-endian*/
160 #define ASI_BLK_AIUS_L_4V 0x1f /* (4V) Sec, user, block, l-endian */
165 #define ASI_BLK_INIT_QUAD_LDD_AIUS 0x23 /* (NG) init-store, twin load,
175 #define ASI_NUCLEUS_QUAD_LDD_L 0x2c /* Cacheable, qword load, l-endian */
177 #define ASI_QUAD_LDD_PHYS_L_4V 0x2e /* (4V) Phys, qword load, l-endian */
179 #define ASI_PCACHE_DATA_STATUS 0x30 /* (III) PCache data stat RAM diag */
180 #define ASI_PCACHE_DATA 0x31 /* (III) PCache data RAM diag */
185 #define ASI_WCACHE_DATA 0x39 /* (III) WCache data RAM diag */
188 #define ASI_QUAD_LDD_PHYS_L 0x3c /* (III+) PADDR, qw-load, l-endian */
195 #define ASI_CORE_RUNNING_W1S 0x41 /* (CMT) LP Running Write-One Set */
196 #define ASI_CORE_RUNNING_W1C 0x41 /* (CMT) LP Running Write-One Clr */
202 #define ASI_LSU_CONTROL 0x45 /* Load-store control unit */
204 #define ASI_DCACHE_DATA 0x46 /* DCache data-ram diag access */
212 #define ASI_ESTATE_ERROR_EN 0x4b /* E-cache error enable space */
215 #define ASI_EC_TAG_DATA 0x4e /* E-cache tag/valid ram diag acc */
217 #define ASI_IMMU 0x50 /* Insn-MMU main register space */
218 #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
219 #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
220 #define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
221 #define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
222 #define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
223 #define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
224 #define ASI_DMMU 0x58 /* Data-MMU main register space */
225 #define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
226 #define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
227 #define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
228 #define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
229 #define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
230 #define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
231 #define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
239 #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */
240 #define ASI_IC_NEXT_FIELD 0x6f /* Insn cache next-field ram diag */
245 #define ASI_EC_DATA 0x74 /* (III) E-cache data staging reg */
246 #define ASI_EC_CTRL 0x75 /* (III) E-cache control reg */
247 #define ASI_EC_W 0x76 /* E-cache diag write access */
251 #define ASI_INTR_DATAN_W 0x77 /* (III) Out irq vector data reg N */
255 #define ASI_EC_R 0x7e /* E-cache diag read access */
261 #define ASI_INTR_DATAN_R 0x7f /* (III) In irq vector data reg N */
265 #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
266 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
267 #define ASI_PST16_P 0xc2 /* Primary, 4 16-bit, partial */
268 #define ASI_PST16_S 0xc3 /* Secondary, 4 16-bit, partial */
269 #define ASI_PST32_P 0xc4 /* Primary, 2 32-bit, partial */
270 #define ASI_PST32_S 0xc5 /* Secondary, 2 32-bit, partial */
271 #define ASI_PST8_PL 0xc8 /* Primary, 8 8-bit, partial, L */
272 #define ASI_PST8_SL 0xc9 /* Secondary, 8 8-bit, partial, L */
273 #define ASI_PST16_PL 0xca /* Primary, 4 16-bit, partial, L */
274 #define ASI_PST16_SL 0xcb /* Secondary, 4 16-bit, partial, L */
275 #define ASI_PST32_PL 0xcc /* Primary, 2 32-bit, partial, L */
276 #define ASI_PST32_SL 0xcd /* Secondary, 2 32-bit, partial, L */
277 #define ASI_FL8_P 0xd0 /* Primary, 1 8-bit, fpu ld/st */
278 #define ASI_FL8_S 0xd1 /* Secondary, 1 8-bit, fpu ld/st */
279 #define ASI_FL16_P 0xd2 /* Primary, 1 16-bit, fpu ld/st */
280 #define ASI_FL16_S 0xd3 /* Secondary, 1 16-bit, fpu ld/st */
281 #define ASI_FL8_PL 0xd8 /* Primary, 1 8-bit, fpu ld/st, L */
282 #define ASI_FL8_SL 0xd9 /* Secondary, 1 8-bit, fpu ld/st, L*/
283 #define ASI_FL16_PL 0xda /* Primary, 1 16-bit, fpu ld/st, L */
284 #define ASI_FL16_SL 0xdb /* Secondary, 1 16-bit, fpu ld/st,L*/
288 #define ASI_BLK_INIT_QUAD_LDD_P 0xe2 /* (NG) init-store, twin load,
291 #define ASI_BLK_INIT_QUAD_LDD_S 0xe3 /* (NG) init-store, twin load,
297 #define ASI_ST_BLKINIT_MRU_P 0xf2 /* (NG4) init-store, twin load,
298 * Most-Recently-Used, primary,
301 #define ASI_ST_BLKINIT_MRU_S 0xf2 /* (NG4) init-store, twin load,
302 * Most-Recently-Used, secondary,
307 #define ASI_ST_BLKINIT_MRU_PL 0xfa /* (NG4) init-store, twin load,
308 * Most-Recently-Used, primary,
309 * implicit, little-endian
311 #define ASI_ST_BLKINIT_MRU_SL 0xfb /* (NG4) init-store, twin load,
312 * Most-Recently-Used, secondary,
313 * implicit, little-endian