Lines Matching +full:0 +full:xf007
56 #define UNALIGN(C) 0
97 for (i = 0; i < 24; i++) { in sh4_translate_init()
153 for (i = 0; i < 32; i++) in sh4_translate_init()
164 qemu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n", in superh_cpu_dump_state()
166 qemu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n", in superh_cpu_dump_state()
168 qemu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n", in superh_cpu_dump_state()
170 for (i = 0; i < 24; i += 4) { in superh_cpu_dump_state()
171 qemu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n", in superh_cpu_dump_state()
176 qemu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
179 qemu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
182 qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n", in superh_cpu_dump_state()
222 return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0; in use_exit_tb()
242 tcg_gen_exit_tb(NULL, 0); in gen_goto_tb()
258 tcg_gen_exit_tb(NULL, 0); in gen_jump()
264 gen_goto_tb(ctx, 0, ctx->delayed_pc); in gen_jump()
279 tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); in gen_conditional_jump()
283 gen_goto_tb(ctx, 0, dest); in gen_conditional_jump()
290 tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1); in gen_conditional_jump()
291 gen_goto_tb(ctx, 0, dest); in gen_conditional_jump()
310 tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1); in gen_delayed_conditional_jump()
321 tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1); in gen_delayed_conditional_jump()
330 tcg_debug_assert((reg & 1) == 0); in gen_load_fpr64()
338 tcg_debug_assert((reg & 1) == 0); in gen_store_fpr64()
343 #define B3_0 (ctx->opcode & 0xf)
344 #define B6_4 ((ctx->opcode >> 4) & 0x7)
345 #define B7_4 ((ctx->opcode >> 4) & 0xf)
346 #define B7_0 (ctx->opcode & 0xff)
347 #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff))
348 #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \
349 (ctx->opcode & 0xfff))
350 #define B11_8 ((ctx->opcode >> 8) & 0xf)
351 #define B15_12 ((ctx->opcode >> 12) & 0xf)
354 #define ALTREG(x) cpu_gregs[(x) ^ ctx->gbank ^ 0x10]
357 #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
413 int opcode = ctx->opcode & 0xf0ff; in _decode_opc()
414 if (opcode != 0x0093 /* ocbi */ in _decode_opc()
415 && opcode != 0x00c3 /* movca.l */) in _decode_opc()
418 ctx->has_movcal = 0; in _decode_opc()
422 #if 0 in _decode_opc()
423 fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode); in _decode_opc()
427 case 0x0019: /* div0u */ in _decode_opc()
428 tcg_gen_movi_i32(cpu_sr_m, 0); in _decode_opc()
429 tcg_gen_movi_i32(cpu_sr_q, 0); in _decode_opc()
430 tcg_gen_movi_i32(cpu_sr_t, 0); in _decode_opc()
432 case 0x000b: /* rts */ in _decode_opc()
438 case 0x0028: /* clrmac */ in _decode_opc()
439 tcg_gen_movi_i32(cpu_mach, 0); in _decode_opc()
440 tcg_gen_movi_i32(cpu_macl, 0); in _decode_opc()
442 case 0x0048: /* clrs */ in _decode_opc()
445 case 0x0008: /* clrt */ in _decode_opc()
446 tcg_gen_movi_i32(cpu_sr_t, 0); in _decode_opc()
448 case 0x0038: /* ldtlb */ in _decode_opc()
452 case 0x002b: /* rte */ in _decode_opc()
461 case 0x0058: /* sets */ in _decode_opc()
464 case 0x0018: /* sett */ in _decode_opc()
467 case 0xfbfd: /* frchg */ in _decode_opc()
472 case 0xf3fd: /* fschg */ in _decode_opc()
477 case 0xf7fd: /* fpchg */ in _decode_opc()
482 case 0x0009: /* nop */ in _decode_opc()
484 case 0x001b: /* sleep */ in _decode_opc()
491 switch (ctx->opcode & 0xf000) { in _decode_opc()
492 case 0x1000: /* mov.l Rm,@(disp,Rn) */ in _decode_opc()
500 case 0x5000: /* mov.l @(disp,Rm),Rn */ in _decode_opc()
508 case 0xe000: /* mov #imm,Rn */ in _decode_opc()
515 if (B11_8 == 15 && B7_0s < 0 && in _decode_opc()
524 case 0x9000: /* mov.w @(disp,PC),Rn */ in _decode_opc()
532 case 0xd000: /* mov.l @(disp,PC),Rn */ in _decode_opc()
540 case 0x7000: /* add #imm,Rn */ in _decode_opc()
543 case 0xa000: /* bra disp */ in _decode_opc()
548 case 0xb000: /* bsr disp */ in _decode_opc()
556 switch (ctx->opcode & 0xf00f) { in _decode_opc()
557 case 0x6003: /* mov Rm,Rn */ in _decode_opc()
560 case 0x2000: /* mov.b Rm,@Rn */ in _decode_opc()
563 case 0x2001: /* mov.w Rm,@Rn */ in _decode_opc()
567 case 0x2002: /* mov.l Rm,@Rn */ in _decode_opc()
571 case 0x6000: /* mov.b @Rm,Rn */ in _decode_opc()
574 case 0x6001: /* mov.w @Rm,Rn */ in _decode_opc()
578 case 0x6002: /* mov.l @Rm,Rn */ in _decode_opc()
582 case 0x2004: /* mov.b Rm,@-Rn */ in _decode_opc()
591 case 0x2005: /* mov.w Rm,@-Rn */ in _decode_opc()
600 case 0x2006: /* mov.l Rm,@-Rn */ in _decode_opc()
609 case 0x6004: /* mov.b @Rm+,Rn */ in _decode_opc()
614 case 0x6005: /* mov.w @Rm+,Rn */ in _decode_opc()
620 case 0x6006: /* mov.l @Rm+,Rn */ in _decode_opc()
626 case 0x0004: /* mov.b Rm,@(R0,Rn) */ in _decode_opc()
629 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
633 case 0x0005: /* mov.w Rm,@(R0,Rn) */ in _decode_opc()
636 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
641 case 0x0006: /* mov.l Rm,@(R0,Rn) */ in _decode_opc()
644 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
649 case 0x000c: /* mov.b @(R0,Rm),Rn */ in _decode_opc()
652 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
656 case 0x000d: /* mov.w @(R0,Rm),Rn */ in _decode_opc()
659 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
664 case 0x000e: /* mov.l @(R0,Rm),Rn */ in _decode_opc()
667 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
672 case 0x6008: /* swap.b Rm,Rn */ in _decode_opc()
675 tcg_gen_bswap16_i32(low, REG(B7_4), 0); in _decode_opc()
676 tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16); in _decode_opc()
679 case 0x6009: /* swap.w Rm,Rn */ in _decode_opc()
682 case 0x200d: /* xtrct Rm,Rn */ in _decode_opc()
692 case 0x300c: /* add Rm,Rn */ in _decode_opc()
695 case 0x300e: /* addc Rm,Rn */ in _decode_opc()
698 t0 = tcg_constant_tl(0); in _decode_opc()
705 case 0x300f: /* addv Rm,Rn */ in _decode_opc()
723 case 0x2009: /* and Rm,Rn */ in _decode_opc()
726 case 0x3000: /* cmp/eq Rm,Rn */ in _decode_opc()
729 case 0x3003: /* cmp/ge Rm,Rn */ in _decode_opc()
732 case 0x3007: /* cmp/gt Rm,Rn */ in _decode_opc()
735 case 0x3006: /* cmp/hi Rm,Rn */ in _decode_opc()
738 case 0x3002: /* cmp/hs Rm,Rn */ in _decode_opc()
741 case 0x200c: /* cmp/str Rm,Rn */ in _decode_opc()
746 tcg_gen_subi_i32(cmp1, cmp2, 0x01010101); in _decode_opc()
748 tcg_gen_andi_i32(cmp1, cmp1, 0x80808080); in _decode_opc()
749 tcg_gen_setcondi_i32(TCG_COND_NE, cpu_sr_t, cmp1, 0); in _decode_opc()
752 case 0x2007: /* div0s Rm,Rn */ in _decode_opc()
757 case 0x3004: /* div1 Rm,Rn */ in _decode_opc()
762 TCGv zero = tcg_constant_i32(0); in _decode_opc()
772 that it is 0x00000000 when adding the value or 0xffffffff when in _decode_opc()
787 case 0x300d: /* dmuls.l Rm,Rn */ in _decode_opc()
790 case 0x3005: /* dmulu.l Rm,Rn */ in _decode_opc()
793 case 0x600e: /* exts.b Rm,Rn */ in _decode_opc()
796 case 0x600f: /* exts.w Rm,Rn */ in _decode_opc()
799 case 0x600c: /* extu.b Rm,Rn */ in _decode_opc()
802 case 0x600d: /* extu.w Rm,Rn */ in _decode_opc()
805 case 0x000f: /* mac.l @Rm+,@Rn+ */ in _decode_opc()
819 case 0x400f: /* mac.w @Rm+,@Rn+ */ in _decode_opc()
833 case 0x0007: /* mul.l Rm,Rn */ in _decode_opc()
836 case 0x200f: /* muls.w Rm,Rn */ in _decode_opc()
846 case 0x200e: /* mulu.w Rm,Rn */ in _decode_opc()
856 case 0x600b: /* neg Rm,Rn */ in _decode_opc()
859 case 0x600a: /* negc Rm,Rn */ in _decode_opc()
861 TCGv t0 = tcg_constant_i32(0); in _decode_opc()
869 case 0x6007: /* not Rm,Rn */ in _decode_opc()
872 case 0x200b: /* or Rm,Rn */ in _decode_opc()
875 case 0x400c: /* shad Rm,Rn */ in _decode_opc()
881 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc()
888 tcg_gen_xori_i32(t0, t0, 0x1f); in _decode_opc()
893 tcg_gen_movi_i32(t0, 0); in _decode_opc()
897 case 0x400d: /* shld Rm,Rn */ in _decode_opc()
903 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc()
910 tcg_gen_xori_i32(t0, t0, 0x1f); in _decode_opc()
915 tcg_gen_movi_i32(t0, 0); in _decode_opc()
919 case 0x3008: /* sub Rm,Rn */ in _decode_opc()
922 case 0x300a: /* subc Rm,Rn */ in _decode_opc()
925 t0 = tcg_constant_tl(0); in _decode_opc()
933 case 0x300b: /* subv Rm,Rn */ in _decode_opc()
951 case 0x2008: /* tst Rm,Rn */ in _decode_opc()
955 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
958 case 0x200a: /* xor Rm,Rn */ in _decode_opc()
961 case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
972 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ in _decode_opc()
984 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
996 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ in _decode_opc()
1010 case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ in _decode_opc()
1028 case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ in _decode_opc()
1032 tcg_gen_add_i32(addr, REG(B7_4), REG(0)); in _decode_opc()
1044 case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ in _decode_opc()
1048 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
1060 case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1061 case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1062 case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1063 case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ in _decode_opc()
1064 case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1065 case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1071 if (ctx->opcode & 0x0110) { in _decode_opc()
1078 switch (ctx->opcode & 0xf00f) { in _decode_opc()
1079 case 0xf000: /* fadd Rm,Rn */ in _decode_opc()
1082 case 0xf001: /* fsub Rm,Rn */ in _decode_opc()
1085 case 0xf002: /* fmul Rm,Rn */ in _decode_opc()
1088 case 0xf003: /* fdiv Rm,Rn */ in _decode_opc()
1091 case 0xf004: /* fcmp/eq Rm,Rn */ in _decode_opc()
1094 case 0xf005: /* fcmp/gt Rm,Rn */ in _decode_opc()
1100 switch (ctx->opcode & 0xf00f) { in _decode_opc()
1101 case 0xf000: /* fadd Rm,Rn */ in _decode_opc()
1105 case 0xf001: /* fsub Rm,Rn */ in _decode_opc()
1109 case 0xf002: /* fmul Rm,Rn */ in _decode_opc()
1113 case 0xf003: /* fdiv Rm,Rn */ in _decode_opc()
1117 case 0xf004: /* fcmp/eq Rm,Rn */ in _decode_opc()
1121 case 0xf005: /* fcmp/gt Rm,Rn */ in _decode_opc()
1129 case 0xf00e: /* fmac FR0,RM,Rn */ in _decode_opc()
1133 FREG(0), FREG(B7_4), FREG(B11_8)); in _decode_opc()
1137 switch (ctx->opcode & 0xff00) { in _decode_opc()
1138 case 0xc900: /* and #imm,R0 */ in _decode_opc()
1139 tcg_gen_andi_i32(REG(0), REG(0), B7_0); in _decode_opc()
1141 case 0xcd00: /* and.b #imm,@(R0,GBR) */ in _decode_opc()
1145 tcg_gen_add_i32(addr, REG(0), cpu_gbr); in _decode_opc()
1152 case 0x8b00: /* bf label */ in _decode_opc()
1156 case 0x8f00: /* bf/s label */ in _decode_opc()
1162 case 0x8900: /* bt label */ in _decode_opc()
1166 case 0x8d00: /* bt/s label */ in _decode_opc()
1172 case 0x8800: /* cmp/eq #imm,R0 */ in _decode_opc()
1173 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s); in _decode_opc()
1175 case 0xc400: /* mov.b @(disp,GBR),R0 */ in _decode_opc()
1179 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); in _decode_opc()
1182 case 0xc500: /* mov.w @(disp,GBR),R0 */ in _decode_opc()
1186 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW | MO_ALIGN); in _decode_opc()
1189 case 0xc600: /* mov.l @(disp,GBR),R0 */ in _decode_opc()
1193 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL | MO_ALIGN); in _decode_opc()
1196 case 0xc000: /* mov.b R0,@(disp,GBR) */ in _decode_opc()
1200 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); in _decode_opc()
1203 case 0xc100: /* mov.w R0,@(disp,GBR) */ in _decode_opc()
1207 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW | MO_ALIGN); in _decode_opc()
1210 case 0xc200: /* mov.l R0,@(disp,GBR) */ in _decode_opc()
1214 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL | MO_ALIGN); in _decode_opc()
1217 case 0x8000: /* mov.b R0,@(disp,Rn) */ in _decode_opc()
1221 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB); in _decode_opc()
1224 case 0x8100: /* mov.w R0,@(disp,Rn) */ in _decode_opc()
1228 tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, in _decode_opc()
1232 case 0x8400: /* mov.b @(disp,Rn),R0 */ in _decode_opc()
1236 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB); in _decode_opc()
1239 case 0x8500: /* mov.w @(disp,Rn),R0 */ in _decode_opc()
1243 tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, in _decode_opc()
1247 case 0xc700: /* mova @(disp,PC),R0 */ in _decode_opc()
1249 tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) + in _decode_opc()
1252 case 0xcb00: /* or #imm,R0 */ in _decode_opc()
1253 tcg_gen_ori_i32(REG(0), REG(0), B7_0); in _decode_opc()
1255 case 0xcf00: /* or.b #imm,@(R0,GBR) */ in _decode_opc()
1259 tcg_gen_add_i32(addr, REG(0), cpu_gbr); in _decode_opc()
1266 case 0xc300: /* trapa #imm */ in _decode_opc()
1276 case 0xc800: /* tst #imm,R0 */ in _decode_opc()
1279 tcg_gen_andi_i32(val, REG(0), B7_0); in _decode_opc()
1280 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1283 case 0xcc00: /* tst.b #imm,@(R0,GBR) */ in _decode_opc()
1286 tcg_gen_add_i32(val, REG(0), cpu_gbr); in _decode_opc()
1289 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0); in _decode_opc()
1292 case 0xca00: /* xor #imm,R0 */ in _decode_opc()
1293 tcg_gen_xori_i32(REG(0), REG(0), B7_0); in _decode_opc()
1295 case 0xce00: /* xor.b #imm,@(R0,GBR) */ in _decode_opc()
1299 tcg_gen_add_i32(addr, REG(0), cpu_gbr); in _decode_opc()
1308 switch (ctx->opcode & 0xf08f) { in _decode_opc()
1309 case 0x408e: /* ldc Rm,Rn_BANK */ in _decode_opc()
1313 case 0x4087: /* ldc.l @Rm+,Rn_BANK */ in _decode_opc()
1319 case 0x0082: /* stc Rm_BANK,Rn */ in _decode_opc()
1323 case 0x4083: /* stc.l Rm_BANK,@-Rn */ in _decode_opc()
1335 switch (ctx->opcode & 0xf0ff) { in _decode_opc()
1336 case 0x0023: /* braf Rn */ in _decode_opc()
1342 case 0x0003: /* bsrf Rn */ in _decode_opc()
1349 case 0x4015: /* cmp/pl Rn */ in _decode_opc()
1350 tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1352 case 0x4011: /* cmp/pz Rn */ in _decode_opc()
1353 tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1355 case 0x4010: /* dt Rn */ in _decode_opc()
1357 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1359 case 0x402b: /* jmp @Rn */ in _decode_opc()
1365 case 0x400b: /* jsr @Rn */ in _decode_opc()
1372 case 0x400e: /* ldc Rm,SR */ in _decode_opc()
1376 tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); in _decode_opc()
1381 case 0x4007: /* ldc.l @Rm+,SR */ in _decode_opc()
1387 tcg_gen_andi_i32(val, val, 0x700083f3); in _decode_opc()
1393 case 0x0002: /* stc SR,Rn */ in _decode_opc()
1397 case 0x4003: /* stc SR,@-Rn */ in _decode_opc()
1437 LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) in _decode_opc()
1438 LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) in _decode_opc()
1439 LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) in _decode_opc()
1440 LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) in _decode_opc()
1441 ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED) in _decode_opc()
1442 LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED CHECK_SH4A) in _decode_opc()
1443 LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) in _decode_opc()
1444 LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) in _decode_opc()
1445 LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) in _decode_opc()
1446 LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) in _decode_opc()
1447 LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED}) in _decode_opc()
1448 case 0x406a: /* lds Rm,FPSCR */ in _decode_opc()
1453 case 0x4066: /* lds.l @Rm+,FPSCR */ in _decode_opc()
1464 case 0x006a: /* sts FPSCR,Rn */ in _decode_opc()
1466 tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff); in _decode_opc()
1468 case 0x4062: /* sts FPSCR,@-Rn */ in _decode_opc()
1473 tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); in _decode_opc()
1480 case 0x00c3: /* movca.l R0,@Rm */ in _decode_opc()
1486 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1491 case 0x40a9: /* movua.l @Rm,R0 */ in _decode_opc()
1494 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1497 case 0x40e9: /* movua.l @Rm+,R0 */ in _decode_opc()
1500 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1504 case 0x0029: /* movt Rn */ in _decode_opc()
1507 case 0x0073: in _decode_opc()
1511 * 0 -> LDST in _decode_opc()
1529 REG(0), ctx->memidx, in _decode_opc()
1534 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1541 tcg_gen_movi_i32(cpu_sr_t, 0); in _decode_opc()
1547 case 0x0063: in _decode_opc()
1552 * occurred 0 -> LDST in _decode_opc()
1560 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1562 tcg_gen_mov_i32(cpu_lock_value, REG(0)); in _decode_opc()
1565 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1567 tcg_gen_movi_i32(cpu_lock_addr, 0); in _decode_opc()
1570 case 0x0093: /* ocbi @Rn */ in _decode_opc()
1575 case 0x00a3: /* ocbp @Rn */ in _decode_opc()
1576 case 0x00b3: /* ocbwb @Rn */ in _decode_opc()
1581 case 0x0083: /* pref @Rn */ in _decode_opc()
1583 case 0x00d3: /* prefi @Rn */ in _decode_opc()
1586 case 0x00e3: /* icbi @Rn */ in _decode_opc()
1589 case 0x00ab: /* synco */ in _decode_opc()
1593 case 0x4024: /* rotcl Rn */ in _decode_opc()
1602 case 0x4025: /* rotcr Rn */ in _decode_opc()
1611 case 0x4004: /* rotl Rn */ in _decode_opc()
1613 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1615 case 0x4005: /* rotr Rn */ in _decode_opc()
1616 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1619 case 0x4000: /* shll Rn */ in _decode_opc()
1620 case 0x4020: /* shal Rn */ in _decode_opc()
1624 case 0x4021: /* shar Rn */ in _decode_opc()
1628 case 0x4001: /* shlr Rn */ in _decode_opc()
1632 case 0x4008: /* shll2 Rn */ in _decode_opc()
1635 case 0x4018: /* shll8 Rn */ in _decode_opc()
1638 case 0x4028: /* shll16 Rn */ in _decode_opc()
1641 case 0x4009: /* shlr2 Rn */ in _decode_opc()
1644 case 0x4019: /* shlr8 Rn */ in _decode_opc()
1647 case 0x4029: /* shlr16 Rn */ in _decode_opc()
1650 case 0x401b: /* tas.b @Rn */ in _decode_opc()
1652 tcg_constant_i32(0x80), ctx->memidx, MO_UB); in _decode_opc()
1653 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cpu_sr_t, 0); in _decode_opc()
1655 case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ in _decode_opc()
1659 case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ in _decode_opc()
1663 case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ in _decode_opc()
1667 if (ctx->opcode & 0x0100) { in _decode_opc()
1678 case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ in _decode_opc()
1682 if (ctx->opcode & 0x0100) { in _decode_opc()
1693 case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ in _decode_opc()
1695 tcg_gen_xori_i32(FREG(B11_8), FREG(B11_8), 0x80000000); in _decode_opc()
1697 case 0xf05d: /* fabs FRn/DRn - FPCSR: Nothing */ in _decode_opc()
1699 tcg_gen_andi_i32(FREG(B11_8), FREG(B11_8), 0x7fffffff); in _decode_opc()
1701 case 0xf06d: /* fsqrt FRn */ in _decode_opc()
1704 if (ctx->opcode & 0x0100) { in _decode_opc()
1715 case 0xf07d: /* fsrra FRn */ in _decode_opc()
1720 case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ in _decode_opc()
1723 tcg_gen_movi_i32(FREG(B11_8), 0); in _decode_opc()
1725 case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ in _decode_opc()
1728 tcg_gen_movi_i32(FREG(B11_8), 0x3f800000); in _decode_opc()
1730 case 0xf0ad: /* fcnvsd FPUL,DRn */ in _decode_opc()
1738 case 0xf0bd: /* fcnvds DRn,FPUL */ in _decode_opc()
1746 case 0xf0ed: /* fipr FVm,FVn */ in _decode_opc()
1756 case 0xf0fd: /* ftrv XMTRX,FVn */ in _decode_opc()
1760 if ((ctx->opcode & 0x0300) != 0x0100) { in _decode_opc()
1769 #if 0 in _decode_opc()
1770 fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n", in _decode_opc()
1868 for (i = 0; i < max_insns; ++i) { in decode_gusa()
1878 i = 0; in decode_gusa()
1881 do { if (i >= max_insns) goto fail; ctx->opcode = insns[i++]; } while (0) in decode_gusa()
1887 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1888 case 0x6000: /* mov.b @Rm,Rn */ in decode_gusa()
1891 case 0x6001: /* mov.w @Rm,Rn */ in decode_gusa()
1894 case 0x6002: /* mov.l @Rm,Rn */ in decode_gusa()
1912 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1913 case 0x6003: /* mov Rm,Rn */ in decode_gusa()
1940 switch (ctx->opcode & 0xf00f) { in decode_gusa()
1941 case 0x300c: /* add Rm,Rn */ in decode_gusa()
1944 case 0x2009: /* and Rm,Rn */ in decode_gusa()
1947 case 0x200a: /* xor Rm,Rn */ in decode_gusa()
1950 case 0x200b: /* or Rm,Rn */ in decode_gusa()
1958 if (op_src < 0) { in decode_gusa()
1973 case 0x6007: /* not Rm,Rn */ in decode_gusa()
1974 if (ld_dst != B7_4 || mv_src >= 0) { in decode_gusa()
1982 case 0x7000 ... 0x700f: /* add #imm,Rn */ in decode_gusa()
1983 if (op_dst != B11_8 || mv_src >= 0) { in decode_gusa()
1990 case 0x3000: /* cmp/eq Rm,Rn */ in decode_gusa()
1994 if ((ld_dst == B11_8) + (ld_dst == B7_4) != 1 || mv_src >= 0) { in decode_gusa()
2002 switch (ctx->opcode & 0xff00) { in decode_gusa()
2003 case 0x8b00: /* bf label */ in decode_gusa()
2004 case 0x8f00: /* bf/s label */ in decode_gusa()
2008 if ((ctx->opcode & 0xff00) == 0x8b00) { /* bf label */ in decode_gusa()
2015 if ((ctx->opcode & 0xf0ff) == 0x0029) { /* movt Rn */ in decode_gusa()
2027 case 0x2008: /* tst Rm,Rn */ in decode_gusa()
2029 if (ld_dst != B11_8 || ld_dst != B7_4 || mv_src >= 0) { in decode_gusa()
2033 op_arg = tcg_constant_i32(0); in decode_gusa()
2036 if ((ctx->opcode & 0xff00) != 0x8900 /* bt label */ in decode_gusa()
2055 switch (ctx->opcode & 0xf00f) { in decode_gusa()
2056 case 0x2000: /* mov.b Rm,@Rn */ in decode_gusa()
2059 case 0x2001: /* mov.w Rm,@Rn */ in decode_gusa()
2062 case 0x2002: /* mov.l Rm,@Rn */ in decode_gusa()
2082 if (st_src == ld_dst || mv_src >= 0) { in decode_gusa()
2156 if (mt_dst >= 0) { in decode_gusa()
2204 ctx->memidx = (tbflags & (1u << SR_MD)) == 0 ? 1 : 0; in sh4_tr_init_disas_context()
2211 (tbflags & (1 << SR_RB))) * 0x10; in sh4_tr_init_disas_context()
2212 ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0; in sh4_tr_init_disas_context()
2298 tcg_gen_exit_tb(NULL, 0); in sh4_tr_tb_stop()
2303 gen_goto_tb(ctx, 0, ctx->base.pc_next); in sh4_tr_tb_stop()