target/riscv/vector_internals.h

2  * RISC-V Vector Extension Internals
4  * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
25 #include "tcg/tcg-gvec-desc.h"
29     if (env->vstart >= vl) {                  \
30         env->vstart = 0;                      \
41  * Note that vector data is stored in host-endian 64-bit chunks,
42  * so addressing units smaller than that needs a host-endian fixup.
49 #define H4(x)   ((x) ^ 1)
63  *      1       000       0
64  *      2       001       1
67  *      -       100       -
68  *     1/8      101      -3
69  *     1/4      110      -2
70  *     1/2      111      -1
98  * Earlier designs (pre-0.9) had a varying number of bits
99  * per mask value (MLEN). In the 0.9 design, MLEN=1.
106     return (((uint64_t *)v0)[idx] >> pos) & 1;  in vext_elem_mask()
111  * Note that when LMUL < 1, the tail includes the elements past VLMAX that
118     uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);  in vext_get_total_elems()
119     int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 :  in vext_get_total_elems()
120                   ctzl(esz) - ctzl(sew) + vext_lmul(desc);  in vext_get_total_elems()
124 /* set agnostic elements to 1s */
137 /* (TD, T1, T2, TX1, TX2) */
155     uint32_t vl = env->vl;                             \
164     for (i = env->vstart; i < vl; i++) {               \
166             /* set masked-off elements to 1s */        \
168                               (i + 1) * ESZ);          \
173     env->vstart = 0;                                   \
174     /* set tail elements to 1s */                      \
182 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP)    \  argument
185     TX1 s1 = *((T1 *)vs1 + HS1(i));                             \
208  * (TX1)(T1)s1 expands the operator type of widen or narrow operations.
210 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP)             \  argument
214     *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1);                      \
232 /* (TD, T1, T2, TX1, TX2) */